With clock rates in the latest CPUs zooming past the 1-GHz barrier and with the onset of Gigabit Ethernet, a major revision of the Peripheral Component Interconnect (PCI) bus specification was clearly needed. Last September, the PCI specification was upgraded to the PCI-X specification. The PCI-X bus architecture calls for significantly higher performance than the earlier PCI version. PCI-X is expected to meet near- and long-term demands for performance scalability because it calls for data throughputs up to 1.066 Gbits/s—an improvement of eight times over the conventional 32-bit, 33-MHz PCI bus. PCI-X stipulates 64-bit as well as 32-bit systems and adapter designs that can operate over the 66- to 133-MHz range. As a result, the new architecture requires advanced design and development test tools.
To meet such requirements, Agilent Technologies has introduced the E2929A PCI-X exerciser/analyzer and the E2922A PCI-X master target test card. This set of tools is intended to validate and debug chip sets, servers, server clusters, RAID systems, and interface cards, as well as other designs using the bus PCI-X interface.
Although the two tools have a number of features in common, they're targeted at different users. The E2929A is aimed more at the design and debug phases (Fig. 1). The E2922A, on the other hand, is configured so that multiples of this test card can be plugged into card slots to behave as exercisers, thereby performing validation and stress tests.
A design verification and diagnostic tool, the E2929A exerciser and analyzer enables fast and predictable debug, optimization, and validation of various PCI-X-based designs (Fig. 2). Suitable environments might be where one wants to connect an external controller to the card, such as a desktop PC running Windows. Configured as a short PCI-X card, the E2929A is simply plugged into the system under test. It can be controlled by an interactive graphical user interface (GUI), or with the addition of an option from a specific customer C program using an open C application programming interface (C-API).
A protocol checker, which is standard in the E2929A, is designed to verify that a design complies with the PCI-X protocol. The checker runs continuously, alerting the designer to PCI-X protocol rule violations in real time. All of the 50 protocol rules, which are derived from the PCI-X specification, are checked concurrently. Any rule can be individually masked to suppress the triggering of known problems.
The E2929A reports errors that occur. Plus, the checker can trigger the optional plug-on PCI state analyzer's trace memory. It also can trigger a FuturePlus PCI-X analysis probe.
The plug-on PCI-X state analyzer with 2 Mbytes of trace memory offers significant trigger and storage qualifier capabilities. This makes it relatively easy to identify complex error conditions. In addition to conventional pattern terms for all PCI-X signals, a bus observer makes the current bus status—address phase, attribute phase, data phase, idle phase, and so on—transparent. As a result, it simplifies the setup of trigger conditions. By combining additional error pattern terms, external trigger inputs, and trigger sequencer capabilities, the E2929A can capture necessary data.
The E2929A PCI-X state analyzer observes all signals, except JTAG, in accordance with the PCI-X specification for a 64-bit 66/100/133-MHz system. It captures 64-bit PCI-X address/data/control signals, PCI-X protocol errors, bus observer signals to decoded bus state signals time-aligned to the bus signals, and active master and target signals aligned with the bus signals, for easy identification of transactions involving the exerciser. Furthermore, it captures four signals from the trigger I/O connector.
Through the use of pushbuttons, the state analyzer storage qualifiers can be programmed, depending on the level of detail necessary, to store all states, to store only particular bus transactions by command type, to suppress idle cycles, or to suppress wait cycles. The plug-on PCI-X state analyzer comes with a Windows-based GUI.
Analysis Probe
For efficient system debugging and software development, the FuturePlus PCI-X analysis probe is the optimal solution whenever X-correlation becomes essential between the PCI-X bus and other system interfaces. For instance, suppose one has to set up a server and wants to figure out what went wrong in the system. This person would want to see what's happening on the CPU bus, as well as on the PCI-X bus.
One would use the PCI-X protocol checker, plugging in the FS2104 FuturePlus logic analyzer link card (available through Agilent as resale part FSI-60042). State analysis could then be performed on the logic analyzer for both the CPU bus and the PCI-X bus.
With the FuturePlus PCI-X Analysis Probe, therefore, the E2929A PCI-X protocol checker becomes an integrated part of the 16700 logic-analyzer system. Additionally, FuturePlus offers a passive probe known as the FS2101. It allows both state and timing analysis with the Agilent 16700 logic-analyzer system.
By simply plugging the Analysis Probe into the E2929A, each PCI-X signal is clocked into the Agilent 16700 logic-analyzer system, together with a protocol-error signal. When the probe is attached, all PCI-X and protocol-error detection signals are clocked through to the logic-analysis system where they are inversely assembled into PCI-X mnemonics.
A fourth E2929A option is a PCI-X exerciser. It can be controlled through a GUI, the command line interface (CLI), or the optional C-API. The CLI runs under Windows 98/2000/NT. This allows the user to interactively control the PCI exerciser and analyzer from an external PC by entering command functions that correspond with the functions provided by the C-API. The CLI can process batch files of concatenated command functions.
The exerciser operates over the 0- to 133.4-MHz range and can emulate and force practically any imaginable behavior from a PCI-X device, except blatant protocol violations. The exerciser comes with a GUI and a CLI. As an option, the exerciser can be controlled from a C-API.