Trailblazing SuperSpeed USB Design And Verification

The more common application for exercisers includes simulating simple bit errors by corrupting the CRC. With intelligent exercisers that can progress through multiple logical states, one can go further and test violations such as corrupting flow control or other link commands. Sending LCRD_A/B/D instead of LCRD_A/B/C/D and similar packet ordering errors should send the link into recovery.

Exercisers should also enable users to easily adjust the timing and frequency of errors to find boundary conditions that might not turn up during simulation. With 20 new state machines and the corresponding substate transitions, the difficulties of creating a comprehensive test plan for USB 3.0 become insurmountable without a protocol-aware exerciser system.

Another concern with testing USB 3.0 is the high data rate and its impact on memory management within analysis equipment. During data transfers, Super- Speed links can flood a typical 1-Gbyte memory space in less than two seconds. Even during link synchronization, a nearly continuous stream of idle and flow control symbols can rapidly consume available capture memory. Event triggering, considered a luxury in USB 2.0, becomes essential with USB 3.0. Snapshot recording or spooling techniques aren’t practical at 5 Gbits/s. Users need the ability to trigger on specific bus conditions or symbols to isolate events of interest.

INDUSTRY ECOSYSTEM
The similarities between SuperSpeed and PCI Express 2.0 have allowed both silicon developers and test vendors to jumpstart their USB 3.0 development. With PCI Express 2.0 IP and expertise under their belt, several silicon design houses are expected to begin sampling USB 3.0 chip sets early in 2009.

Likewise, both electrical and protocollayer test vendors have leveraged their PCI Express 2.0 techniques to deliver stable tools well ahead of the mainstream market. Nowhere is this more evident than in the critical signal-locking performance of these early analyzers.

Custom circuitry leveraged from PCI Express 2.0 analyzers has been adapted to USB 3.0 testers to provide impressive signal fidelity. This allows the analyzer to sit in the data path and seamlessly recover from electrical idle and capture the linktraining sequence. All training parameters, including timing elements, are reported in the trace, as are individual bus and power state transitions.