If the cursors are moved from one cache-read cycle to the next, the measurements show a small difference in rise time between two data bits. The falling edges of the data bits are of great interest, because they exhibit a significant difference of more than 3 ns. Oddly enough, it is also apparent that there is no undershoot on D4 during cache reads.
It often proves helpful to quantify, and develop an understanding of, the repetitive nature of the problem. Modern scopes provide powerful statistical analysis capacities. In addition, they have the processing power to collect automated parameter measurement statistics on selected parameters over many sweeps, as shown in Figure 7.
Over time, the average difference in fall time between the two data bits is approximately 3.8 ns (11.82 - 8.04). The standard deviation of the measured delay is relatively low, indicating that the cause of the problem is very stable.
Based on the visual, parametric, and statistical results collected, it appears that the problem is due to the pc board itself. Sure enough, a check of the trace for D4, between the SRAM and the CPU, indicates an impedance of greater than 200Ω! This high value explains both the extended fall time and the reduced undershoot. A jumper wire is used to bypass the suspected trace, and the failure is eliminated.
A microprocessor-based system, similar to the one in the first example, fails intermittently and generates sporadic DRAM parity errors. The failures appear to be unrelated to the operating mode, and the memory diagnostic indicates seemingly random single- and multiple-bit errors.
The DRAM data and address buses are examined at the various failure points indicated by the diagnostic. A logic analyzer is used to verify important control signals, while observing the buses. Yet, there is no indication of any logic-related problems. Repetitive reading and writing to the failing locations does not provide any additional insight.
The evidence thus far leads to the conclusion that the failure may be noise-related. To gain additional insight, the multiplexed address bus is examined using a DSO, which can better measure the characteristics of the non-repetitive bus signals.
An LC574 scope, with LeCroy's Smart Trigger capability, is used for further investigation. The interval trigger mode is selected to trigger the DSO when the interval between negative edges on the address bus is less than or equal to 55 ns—slightly less than two bus clocks. Address signals will not normally change states in less than two clock cycles unless there is a problem, which will trigger the scope. With this trigger setup, each address line is probed until one triggers the scope—indicating a potentially problematic address line.
Figure 8 shows an Analog Persistence display of (from top to bottom) the 33-MHz bus clock, the low-asserted column address strobe (—CAS), address bit A1, and address bit A0.
The unusual perturbations on address line A0 (shown in trace 4) appear to be a problem. The perturbations, or bumps, occur when —CAS is asserted As shown by the amplitude cursor, they appear to exceed 2.0 V in some cases. Bit A1 (shown in trace 3) exhibits proper behavior.
LeCroy's Analog Persistence mode displays the events occurring most frequently with the highest trace intensity, as well as those occurring least frequently with the least intensity—similar to an analog scope display. The problem is easily seen with this approach, but the cause is not yet understood. Whether the observed glitches are a result of transmission-line effects, ringback, coupling, or another factor must still be determined.
The appearance of glitches prompts the decision to use a glitch trigger, with suitable values for pulse duration (<12.5 ns) and level (0.5 V). While it is difficult to maintain a stable display by triggering in this manner, the use of the sequence mode makes it possible to capture a number of signal segments for closer examination.
Sequence mode, along with this DSO's long record length, enables the capturing of up to 2000 segments in single-shot mode, minimizing acquisition dead time. The data, as well as the trigger time for each sequence, is stored, providing valuable debug information. Each segment contains glitches that satisfy the glitch trigger condition (Fig. 9).
Zoom trace A is used to closely examine each of the captured segments to determine which ones contain the "problem" glitch. Note that the peak of the highlighted glitch is over 2 V.
The DSO's status display indicates the time at which each of the segments was acquired (Fig. 10). From the times displayed, a correlation is immediately apparent. Many of the segments occur at relative times, which are multiples of 16 ms—the DRAM refresh period. Based on these results, the DRAM controller is carefully evaluated and replaced, eliminating the problem.
Most scopes with adequate bandwidth may be used to debug simple timing problems. Debugging nonrepetitive bus operations requires the single-shot acquisition capability of a DSO, with sufficient sample rate to view signal details.
Color-graded, as well as persistence displays, can be used effectively to view anomalies on digital buses. And it would be difficult to characterize glitches and infrequent and unique events without the powerful triggering capability of a modern DSO. Also necessary are automated parameters measurements, parameter statistics, and time stamping.
If the cursors are moved from one cache-read cycle to the next, the measurements show a small difference in rise time between two data bits. The falling edges of the data bits are of great interest, because they exhibit a significant difference of more than 3 ns. Oddly enough, it is also apparent that there is no undershoot on D4 during cache reads.
It often proves helpful to quantify, and develop an understanding of, the repetitive nature of the problem. Modern scopes provide powerful statistical analysis capacities. In addition, they have the processing power to collect automated parameter measurement statistics on selected parameters over many sweeps, as shown in Figure 7.
Over time, the average difference in fall time between the two data bits is approximately 3.8 ns (11.82 - 8.04). The standard deviation of the measured delay is relatively low, indicating that the cause of the problem is very stable.
Based on the visual, parametric, and statistical results collected, it appears that the problem is due to the pc board itself. Sure enough, a check of the trace for D4, between the SRAM and the CPU, indicates an impedance of greater than 200Ω! This high value explains both the extended fall time and the reduced undershoot. A jumper wire is used to bypass the suspected trace, and the failure is eliminated.
A microprocessor-based system, similar to the one in the first example, fails intermittently and generates sporadic DRAM parity errors. The failures appear to be unrelated to the operating mode, and the memory diagnostic indicates seemingly random single- and multiple-bit errors.
The DRAM data and address buses are examined at the various failure points indicated by the diagnostic. A logic analyzer is used to verify important control signals, while observing the buses. Yet, there is no indication of any logic-related problems. Repetitive reading and writing to the failing locations does not provide any additional insight.
The evidence thus far leads to the conclusion that the failure may be noise-related. To gain additional insight, the multiplexed address bus is examined using a DSO, which can better measure the characteristics of the non-repetitive bus signals.
An LC574 scope, with LeCroy's Smart Trigger capability, is used for further investigation. The interval trigger mode is selected to trigger the DSO when the interval between negative edges on the address bus is less than or equal to 55 ns—slightly less than two bus clocks. Address signals will not normally change states in less than two clock cycles unless there is a problem, which will trigger the scope. With this trigger setup, each address line is probed until one triggers the scope—indicating a potentially problematic address line.
Figure 8 shows an Analog Persistence display of (from top to bottom) the 33-MHz bus clock, the low-asserted column address strobe (—CAS), address bit A1, and address bit A0.
The unusual perturbations on address line A0 (shown in trace 4) appear to be a problem. The perturbations, or bumps, occur when —CAS is asserted As shown by the amplitude cursor, they appear to exceed 2.0 V in some cases. Bit A1 (shown in trace 3) exhibits proper behavior.
LeCroy's Analog Persistence mode displays the events occurring most frequently with the highest trace intensity, as well as those occurring least frequently with the least intensity—similar to an analog scope display. The problem is easily seen with this approach, but the cause is not yet understood. Whether the observed glitches are a result of transmission-line effects, ringback, coupling, or another factor must still be determined.
The appearance of glitches prompts the decision to use a glitch trigger, with suitable values for pulse duration (<12.5 ns) and level (0.5 V). While it is difficult to maintain a stable display by triggering in this manner, the use of the sequence mode makes it possible to capture a number of signal segments for closer examination.
Sequence mode, along with this DSO's long record length, enables the capturing of up to 2000 segments in single-shot mode, minimizing acquisition dead time. The data, as well as the trigger time for each sequence, is stored, providing valuable debug information. Each segment contains glitches that satisfy the glitch trigger condition (Fig. 9).
Zoom trace A is used to closely examine each of the captured segments to determine which ones contain the "problem" glitch. Note that the peak of the highlighted glitch is over 2 V.
The DSO's status display indicates the time at which each of the segments was acquired (Fig. 10). From the times displayed, a correlation is immediately apparent. Many of the segments occur at relative times, which are multiples of 16 ms—the DRAM refresh period. Based on these results, the DRAM controller is carefully evaluated and replaced, eliminating the problem.
Most scopes with adequate bandwidth may be used to debug simple timing problems. Debugging nonrepetitive bus operations requires the single-shot acquisition capability of a DSO, with sufficient sample rate to view signal details.
Color-graded, as well as persistence displays, can be used effectively to view anomalies on digital buses. And it would be difficult to characterize glitches and infrequent and unique events without the powerful triggering capability of a modern DSO. Also necessary are automated parameters measurements, parameter statistics, and time stamping.