When designing digital video systems, a significant amount of time is spent searching the display for any instabilities arising from noise, cross-talk, or timing violations. These problems become even more difficult if the system contains compression, graphics processors, coders, decoders, or links working close to their maximum performance.
The suggested circuitry replaces the video signal with the checksum of itself, counting from the start of the frame down to the last pixel of the last line (see the figure).
A steady video signal will then show a stable and deterministic noise pattern.
Any single-bit error or minute variation in the video signal will change the noise pattern (actually the CRC values) from that point through the rest of the frame. Considering that the eye is very sensitive to change, it's impossible to miss the error or its position.
This design relies on the fact that linear feedback shift registers (LFSR) are used for generating checksums (CRC) as well as producing pseudo-random sequences. For a good paper on the background of CRCs and their implementation in FPGAs, go to www.cypress.com/pub/appnotes/crc.pdf.
A CRC of any length with an 8-bit input can be employed. This arrangement uses a 10-bit LFSR with taps on bit 2 and bit 9, since fewer taps makes the logic simpler. Depending on the internal architecture of the FPGA used, the design fits into one or two layers of lookup tables, making it compact and fast (see the listing).