Adnan Hamid

Adnan
Hamid
CEO,
Breker Verification Systems

Adnan Hamid is cofounder and CEO of Breker Verification Systems. Prior to starting Breker in 2003, he worked at AMD as department manager of the System Logic Division. Previously, he served as a member of the consulting staff at AMD and Cadence Design Systems. He graduated from Princeton University with BS degrees in electrical engineering and computer science and holds an MBA from the McCombs School of Business at the University of Texas. He can be reached at adnan@brekersystems.com. 

Articles
Complex Chip Designs Need System-Level Scenario Coverage
Today's coverage technology exists today to create scenario models; automatically generate coverage goals; automatically generate test cases to hit those goals; and combine system-level metrics with traditional forms of coverage for a comprehensive view of verification.
Automatically Generated C Test Cases Earn a Solid Return on Investment

In the history of functional verification for complex chips, increasing automation has replaced tedious and expensive manual effort.

The Fundamentals Of Thread Visualization For Test Case Understanding And Debug 1
Automating the handwritten C tests that run on the SoC’s embedded processors will increase team productivity and foster reuse throughout the project.
The Verification Flow Can Enable Horizontal Reuse
Today's EDA companies now face the primary need for a verification flow that enables complete horizontal reuse of verification environments from concept to silicon and beyond.
Interview: Adnan Hamid Addresses Trends In Chip Verification
Adnan Hamid, cofounder and CEO of Breker Verification Systems, talks with Technology Editor Bill Wong about challenges with SoC verification.
Remove The Processor Dilemma From Constrained-Random Verification
UVM testbenches for blocks are adequate until the stage of a subsystem with one or more processors. The new generation of constrained-random test cases based on scenario models can take it from there.
One Verification Model To Drive Them All
Given that the constrained-random approach cannot adequately address SoC verification, there’s an opportunity to redesign functional verification and to unify many aspects of a verification flow into a single coherent description.
Surveying The Verification Landscape
Most companies use a bottom-up verification flow, which has some implications on the tools that they use for verification. Some companies, though, are moving to a top-down flow because today’s systems involve more than hardware.
Sizing Up The Verification Problem
Some pundits say the number of vectors required to verify an SoC is greater than the number of stars in the universe. This is poppycock! The total number of vectors necessary can be substantially reduced in a number of areas.
Commentaries and Blogs
Guest Blogs
Jan 4, 2016
blog

Building Home or Very Small Office Electronic Circuit Prototypes, Part 3 6

Part 3 delves into critical equipment for testing today's electronics, and provides updates on circuit-board designs from Part 1....More
Nov 16, 2015
Commentary

Building Home or Very Small Office Electronic-Circuit Prototypes, Part 2 6

Part 2 gives step-by-step instructions on how to turn a Black & Decker TO1675B convection countertop oven into a temperature-controlled reflow oven....More
Oct 7, 2015
Commentary

Building Home or Very Small Office Electronic-Circuit Prototypes, Part 1 17

This first part in a series goes through the steps of creating a preliminary design for a small and inexpensive hobbyist/limited-technology-prototype build-and-test capability....More

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