Lauro Rizzatti

Lauro
Rizzatti
Consultant

Lauro Rizzatti is a verification consultant. He was formerly general manager of EVE-USA and its vice president of marketing before Synopsys’ acquisition of EVE. Previously, he held positions in management, product marketing, technical marketing, and engineering. He can be reached at lauro@rizzatti.com.  

Articles
Moving to Deterministic ICE
A happy medium between in-circuit emulation (ICE) and a virtual environment with software-based test perhaps exists with Deterministic ICE.
11 Myths About Hardware Emulation
These 11 myths about hardware emulation shed light on misconceptions and falsehoods surrounding the EDA technology.
Implementing Functional Coverage with Hardware Emulation
By preserving capacity without sacrificing coverage, verification engineering teams get comprehensive functional verification with minimal incremental effort and without a hit on emulation capacity.
Emulation Fast-Tracks Networking Products to Market
An Ethernet VirtuaLAB provides a software-controlled environment for generating, transmitting, and analyzing Ethernet packets to test Ethernet SoCs mapped inside an emulation platform.
Speeding Mobile Products to Market
By switching to an emulation-based methodology, a company developing application processor units (APUs) can bring up the design on the emulator in days, and typical design changes can be accommodated in less than a day.
The Melting of the ICE Age
Many designers still use ICE, but a designer’s verification perspective typically changes once he or she experiences transaction-based verification through emulation.
Point/Counterpoint: Hardware Emulation’s Versatility
Hardware emulation or FPGA prototyping? Electronic Design called on verification expert Dr. Lauro Rizzatti and S2C chairman and CTO Mon-Ren Chene to make their cases as to which is the best solution for complex SoC verification.
Hardware Emulation: A Weapon of Mass Verification
Greater time-to-market pressures, along with escalating hardware/software integration and quality concerns, make the verification process a strategically important step in chip design. Coming to the rescue is a new generation of cost-effective hardware emulators.
Emulation Design Datacenters Support Verification Engineers
Emulation allows the register transfer level (RTL) source code to be used as the model but with enough processing performance to enable system-level work, especially when it involves software development or running software workloads.
What’s The Difference Between FPGA And Custom Silicon Emulators?
The fundamental difference between commercial FPGA-based emulators and emulators based on custom silicon lies in the core element that maps the design-under-test (DUT).
Four Technologies Converge In Hardware Emulation
Metaphorically speaking, a hardware emulation system sits on four technological pillars: the hardware, the compiler, the run-time environment, and the supporting verification intellectual properties, or VIPs.
Finding A Bug In The SoC Haystack
Finding critical bugs in the interaction of the embedded software running with the underling hardware is like finding the proverbial needle in a haystack. Finding problems quickly in the course of running billions and trillions of cycles of operation requires unique hardware debug tools and a rigorous tracing methodology.
Power Trumps Performance In Today’s SoC Designs
As the mainstream process node moves to 40 nm and as 28-nm, 20-nm, and 14-nm finFETs gain momentum, the largest designs are approaching billion-gate capacities. These trends make power-aware verification and switching activity tracking for power estimation extremely compute-intensive tasks that can only be addressed by the latest generations of emulators.
Commentaries and Blogs
Guest Blogs
Apr 8, 2016
Commentary

Confabbing on the Fabless Fad 3

High capital and maintenance costs, and EDA advances along with abstractions to deal with chip complexity, have been leading contributors to the fabless migration....More
Mar 2, 2016
Article

Home or Very Small Office Electronic Circuit Prototypes, Part 4 5

Part 4 focuses on testing for a reflow oven and build of a mixed SMT/through-hole board....More
Jan 4, 2016
blog

Building Home or Very Small Office Electronic Circuit Prototypes, Part 3 11

Part 3 delves into critical equipment for testing today's electronics, and provides updates on circuit-board designs from Part 1....More

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