In today's established dual-front wiper systems, a mechanical link between the left and right wiper is used for synchronization (Figure 1). This is necessary because of the different behaviors of the wipers due to dirt on the windshield, the effects of wind, or the condition of the wiper. For many years, the automotive industry has been looking for an intelligent solution to reduce the noise and space demands of the mechanical link.
One solution is the replacement of the mechanical linkage by an electronic one (Figure 2). In this architecture, a dc motor powers each wiper. The dc motors are controlled by a microcontroller and a driver IC, which can be mounted directly inside the motor assembly. An interface handles the synchronization between the left and right wiper, so that no mechanical link between the wipers is necessary as with conventional wiper systems, achieving considerable noise and space reduction.
For cost reasons, dc motors are used in wiper systems. A full H-bridge gate driver supporting PWM and direction-controlled driving of four power MOSFETs can control this type of motor. An IC for this application must be designed in a high-voltage process and must be suitable for use in harsh environments. Also, an optimized communication interface is necessary for a high-volume dc-motor application such as the windshield wiper system.
Because the wiper electronics are usually located close to the car radio, the EMC emissions have to be controlled — the eclectic disruption of the car radio would be uncomfortable for the car driver. A differential serial communication interface (SCI) transceiver can be used to reduce these radiation emissions for improved EMC performance. The SCI transceiver is a differential device that can also operate in single-ended mode for systems with only one wiper. The SCI functionality makes this gate driver similar to LIN devices. Compared to standard LIN interfaces, however, a faster data transfer of up to 100 kbaud is possible.
Each wiper module (Figure 3) consists of a microcontroller, a highly integrated gate driver and the dc motor. Several Hall sensors measure the positions of the two wipers. The driver sends the commands via the wiper switches to the microcontroller. The electronics can be mounted close to the wiper motor without any huge space demand.
The importance of low current consumption of an ECU continues to grow. To be able to guarantee the low quiescent current of the inactive IC, a dedicated wake-up and sleep mode strategy is required. A typical partitioning of a wiper application is shown in Figure 4. It consists of the microcontroller, the voltage regulator supplying the microcontroller, and other discrete elements, e.g., Hall sensors. For safety reasons — it would be critical if a wiper failed while driving in the rain — a watchdog in the system is required.
To further guard against failure, an automotive IC requires features such as overtemperature shutdown, overvoltage and undervoltage protection, as well as full protection against short circuits, and meeting strict automotive qualification demands (protection against conducted interference, EMC and ESD protection). To solve these problems and meet the above requirements, Atmel has created a highly integrated gate driver IC, the ATA6026. This gate driver IC includes a 5 V/100 mA voltage regulator plus a watchdog, resulting in fewer external components for smaller designs requiring less PCB area — a critical issue in mechatronic solutions. The IC carries out the motion control, so this function does not need any additional memory in the microcontroller. The watchdog is implemented as a window watchdog and will be triggered by the microcontroller via a low to high transition at pin WD during the open window. If the watchdog detects a window error — no trigger in the open window or a false trigger in the closed window — a reset pulse will be generated.
The block diagram in Figure 5 shows the implemented functions and the typical application schematic. The microcontroller controls the driving function of the IC by providing a PWM speed signal and a direction signal. Because this chip has to drive the gates of the external H-bridge, it includes two push-pull drivers to control two external power NMOS FETs used as high-side drivers and two push-pull drivers to control two external power NMOS FETs used as low-side drivers. The drivers can be used with standard or logic-level power NMOS FETs. The drivers for the high-side control use external bootstrap capacitors to supply the gates with a voltage of 8 V to 14 V above the battery voltage level. It is also possible to control the motor in the reverse direction. A duty cycle of 100% in both directions is possible by using the charge pump to supply the gates of the high-side drivers. To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS transistors is implemented. An external RC combination defines the cross-conduction time.
The low-power and low-drop on-chip voltage regulator is used for the internal and external voltage supply. An external transistor as a power element helps to reduce power dissipation. When inactive, the device's sleep mode guarantees a low quiescent current of typically 35 microamperes. For a battery voltage level between 6 V and 9 V the regulated output voltage is 5 V ± 10%, above 9 V the regulated output voltage is 5 V ± 3%. To prevent destruction of external NPN and of the IC, a sense resistor is used to detect the current delivered by the regulator. In case of overcurrent, the regulator limits the current to the specified level. This means if the characteristic of the voltage regulator changes to one of a current regulator, the delivered voltage will break down. The fully integrated charge pump supplies the gates of the external power MOSFETs of the high side drivers in case of a permanent ON state (100% PWM, the bootstrap function is not available). In addition, the gate of an external power NMOS used for reverse battery protection may be supplied by the charge-pump output.
As mentioned earlier, ECU applications need sleep-mode functionality to meet the low current- consumption requirement. During the ATA6026's sleep mode, it is possible to wake up the IC by using the pin EN or data. Only a few blocks are awake (the band gap, the internal 5 V regulator with 100 nF external blocking capacitor, the input structure for detecting the EN pin threshold and the wake-up block of the SCI receive part). The default state after power on is the active mode. To change between the two modes, three procedures are implemented. In addition to the activation/deactivation of the EN pin there is a second possibility for waking up by using the SCI transceiver. In sleep mode the SCI receiver is partially active and works in single-ended mode. If using the SCI for going to active, the EN pin can remain low without disturbing the active mode.
Due to the monolithic integration of the voltage regulator, motion control, watchdog and the communication interface in one small QFN package, overall system costs can be reduced while maintaining the flexibility of the output stages for plug-and-play use in almost any kind of motor-driver application without needing adaptation. The motion control is part of the IC, only the PWM speed signal and the direction information has to be provided by the microcontroller. Two diagnosis pins enable the possibility for fail-safe functions.
ABOUT THE AUTHOR
Carsten Eschert studied electrical engineering with a focus on communications engineering at the University of Applied Sciences in Lübeck, Germany. After seven years working as a design engineer and marketing manager in the semiconductor industry, he moved to Atmel Germany GmbH in 2004. He works in product marketing in the Automotive Mixed Signals area where he is responsible for smart power drivers and network devices.