Clearly, many of today’s innovations in automobile design result from the growing demand for more electronics within the car. Cars now come with state-of-the-art audio and video systems, high-tech and graphic-rich navigation systems, and wireless technologies for many types of communications.
Safety electronics should make a quantum leap forward with advanced driver assistance systems (ADASs), which are involved with braking, steering, and collision avoidance. When drivers become distracted, the risk of an accident quickly increases. In 2008 alone, according to the National Highway Traffic Safety Administration (NHTSA), 6000 Americans died due to a distracted driver and another 500,000 were injured.
Automakers are now turning their attention to accident prevention, with a focus on improving the driver’s experience. To lessen distractions, key vehicle and driving information needs to be displayed in front of the driver, specifically in the dashboard.
The instrument cluster, a space once reserved for electromechanical gauges and light indictors, is transforming into a new digital information center for drivers. Thanks to the advancement and maturing reliability of digital thin-film-transistor (TFT) displays, improved signal processing power, and high-speed digital communication, analog-based systems are rapidly migrating to digital system displays.
Today’s dashboards built around TFT displays still provide basic vehicle information, such as drive train position, speed, fuel levels, and engine status, while bringing in additional data from outside the car. This added information comes from new innovations like 360° cameras, night vision, lane-departure warning, blind-spot detection, and 3D graphic navigation data.
Digital clusters enable a more cost-effective and flexible means to converge all vehicle and safety information, which further minimizes any unnecessary distractions. The driver no longer needs to look down or fumble with the center console searching for music, make phone calls, look up driving directions, or turn one’s head to look at a blind spot.
While these new advances offer many new and exciting options, they also require designers to find innovative solutions to control costs as well as deliver critical performance capabilities and ensure long-term product reliability. This article will present some automotive design/reliability constraints, a review of digital cluster architectures, and reasons why memory subsystem tradeoffs may impact your next project’s performance, reliability, and cost.
Digital-Cluster Design Challenges
Digital clusters must support high-performance, real-time processing requirements (e.g., existing consumer-based display platforms) while exponentially increasing the design’s long-term reliability. Automotive-market OEMs (original equipment manufacturers), tier-one suppliers, and customers will not accept display malfunctions as a simple inconvenience, much like those typically associated with consumer-based phones or PCs.
The new digital cluster is creating a user-friendly, non-distractive, and informative environment to promote safer driving. It must deliver these high-performance levels and provide long-term operational reliability while operating in very demanding and harsh operating conditions (such as extreme temperatures of -40°C to +105°C). These stringent automotive environmental, safety, and quality requirements drive long development cycles—sometimes extending to three or more years—before the display technology debuts in a car.
Automotive designs follow very methodical planning, design, and verification practices to identify and mitigate operational or reliability issues. As part of this process, an automotive designer often selects electronics suppliers that develop their products using high-quality design methodology, such as TS16949, and qualify them to meet the Automotive Electronics Council’s (AEC) stringent AEC-Q100 standards.
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Once a supplier releases a system to production, component suppliers must continuously monitor their internal and external reliability performances and implement required corrective actions to reach zero defective parts per million (dppm) goals. OEMs and tier-one suppliers also expect their supply base to provide long-term product support and availability. After an automotive embedded system is deployed, it’s typically cost-prohibitive and sometimes not possible to revalidate a design to support components with short life cycles. In some cases, the cost of revalidation can be in the hundreds of thousands of dollars.
The latest digital clusters use greater amounts of graphic-intensive content, resulting in a more sophisticated informative display system with added levels of functionality. Still, it must reliably fulfill the fundamental objective to inform the driver of basic vehicle and safety information.
For example, a digital cluster must provide the current car status almost instantly during vehicle “Key On.” Usually, this involves the display of critical drive-train position information (i.e., P R D 1 2 3) on the TFT in less than one second. Thus, an almost instant cluster turn-on is essential, which in turn requires designers to investigate critical system- and component-level performance capabilities. Even providing what appears to be simplistic information, such as a low tire-pressure warning prior to initiating a trip, proactively mitigates potential safety issues.
Finding Reliable Solutions
As noted earlier, the cluster migration from analog- to digital-based systems creates more complexity. Consequently, it’s pushing designers to develop innovative solutions that address competing system requirements, such as real-time performance, long-term high reliability, and reduced costs. We will look at how this basic information can be provided in a reliable but cost effective manner.
In a typical high-level digital cluster, an automotive centric system-on-a-chip (SoC) substantially derives input data for driving the TFT display through its communication network and internal or external memory (Fig. 1). These digital clusters employ architectures that are similar to many high-performance, consumer-based display systems. Both automotive and consumer display platforms now require high-density memory to support their substantial digital content. For instance, the density requirement could be as high as 2 Gbits for high-resolution large displays with 3D graphic content and 32-bit color.
This content typically consists of large character sets, multiple fonts, graphic images, and extended support for multiple languages to create the informative display system. A digital-cluster frame buffer is generated and displayed via industry-standard techniques. The SoC display controller renders one frame on the system display; in parallel, the SoC/graphics engine accesses internal or external memory to obtain, process, and store the next set of data in the frame buffer for subsequent display. Today’s SoCs require high bandwidth access to reliable code and data residing in external memory to enable fast system startups and high-speed real-time processing.
Memory Architecture And Subsystem Tradeoffs
Memory architecture and design implementation can have a major effect on an embedded system’s performance. To understand its impact, it’s best to review a couple of memory architectures that illustrate certain performance/cost tradeoffs when using today’s technology.
First, let’s take a look at a standard code-shadowing memory architecture, which is very typical for a high-performance embedded-display system (Fig. 2). The system controller or general processing unit (GPU) has a high level of integration, including graphics engines, display controllers, options for limited embedded RAM, and flash, while continuing to offer external memory interfaces to support a digital cluster’s high-performance and high-density memory requirements.
The external memory falls into two standard offerings—DRAM and dlash. The embedded system startup is highlighted by a three-step process: code/data shadowing from flash to DRAM; initialization of the processor, DRAM, and other key components; and then execution of the application. Once code execution begins, useful information can be displayed.
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There are a couple of key takeaways with this architecture. First, the SoC/DRAM high-speed access capabilities facilitate the high-performance real-time capabilities. Second, the system’s initial startup time is considerably defined by the shadowing and initialization times. SoC/flash access bandwidths and the data densities transferred from flash to DRAM characterize the shadowing time.
Today, flash suppliers offer multiple nonvolatile-memory (NVM) technologies. Two of the most widely used technologies are NOR and NAND flash. Each provides different features, such as access capabilities, reliability levels, product life cycles, and cost. Automotive SoCs typically support multiple interface configurations to access external parallel and serial NOR flash, while NAND flash interfaces continue to garner increased support.
One very dynamic variable for the SoC NAND interface involves defining the required level of ECC support, especially given NAND’s fast lithography migrations. On the NOR side, Page flash and synchronous NOR flash meets these stringent automotive requirements. For example, a new high-end digital cluster design like the Volt’s E-Flex cluster uses Freescale’s MPC5121e SoC and Spansion’s S29GL512N flash. The Spansion GL Page Read access enables high-speed read access, as fast as 80-Mbyte/s throughput, to facilitate the Volt’s E-Flex requirement to display drive train position (i.e. P R D 1 2 3) in less than one second at “Key On.”
Some of the latest innovations by automotive chip-set and flash suppliers have brought about new cost-savvy, hybrid digital-cluster architectures (Fig. 3). The system controller (Freescale Spectrum) and flash (Spansion Multi I/O SPI) make it possible to optimize the TFT display architecture, delivering a more cost-effective entry-level instrument cluster solution. The system controller executes code from embedded flash, while loading graphics data from external flash via the high-bandwidth Multi I/O SPI protocol. Graphics data is processed and stored in the internal frame buffer, which is directly displayed on a TFT. This hybrid architecture meets system performance and reliability requirements, and saves cost since there’s no need for external DRAM support.
This application architecture can require hundreds of millions of read cycles that affect the viable use of technologies like NAND. However, current NAND devices can exhibit additional bit disturb errors when used in applications that have mid- to high-read cycling applications.
The new Multi I/O SPI communications protocol is used for data transfers between the system controllers and external SPI flash. Accesses to Multi I/O SPI, which is based on the popular Serial Peripheral Interface (SPI), can be configured to support one to four data connections. This feature improves previous SPI access capabilities from less than 10 Mbytes/s up to approximately 40 Mbytes/s.
Automotive chipset and flash suppliers, such as Freescale and Spansion, offer standard products that designers can use to exploit Multi I/O SPI-improved access bandwidths, leading to improved cost points and high-performance digital clusters. In some cases, two Quad I/O SPIs are being used to support up to 80 Mbytes/s of continuous throughput.
Spansion’s Multi I/O SPI FL family still supports the low-pin-count serial interface while supporting improved read bandwidths that are comparable to today’s higher-pin-count flash devices. The family also supports mid- to high-density requirements, long-term data integrity, and full device operation up to +105°C, and it’s AEC-Q100 qualified.
Ken Perdue, field application engineer MTS, holds a BSEE (Purdue degree) from Indiana University Purdue University at Indianpolis (IUPUI).