Confabbing on the Fabless Fad

High capital and maintenance costs, and EDA advances along with abstractions to deal with chip complexity, have been leading contributors to the fabless migration.

“Real men have fabs.”  Jerry Sanders—AMD founder (circa 1993)

This quote made a lot of sense for AMD, being one of Intel’s main competitors at the time. But for other fresh startup companies in the mid-1980s, this wasn’t quite the case. Owning a fab wasn’t as easy as getting abs.

For instance, capital and maintenance costs were big hurdles, not to mention the additional cost of improving the manufacturing equipment and machines (remember Moore’s Law). Also, the transition from fab to fabless for already existing semiconductor companies can’t happen overnight. There was the issue concerning design architecture and compatibility, the conflict with the ASIC model, and the lack of investors due to the outrageousness of the concept.

These issues were resolved with innovations in EDA and the publication of “Introduction to VLSI Systems” (that lead to the creation of simplified abstractions to manage chip design complexity), aaaand… the fabless fad was on.

The Pros and Cons of a Fabless Model

Nowadays, a fab can be worth as much as $10 billion, with most of the cost attributed to the spontaneous change in process development. The price is so high that only Intel and TSMC have modern fabs today. No wonder Bernie Vonderschmitt of Xilinx and Gordon Campbell of Chips and Technologies envisioned a semiconductor company thriving without one.

As Bernie vowed, “If I ever start a semiconductor company, it will be fabless.” And so in 1984, Xilinx became the first fabless company to specialize in FPGAs, while Chips and Technologies became the first fabless company to specialize in graphic chips for PCs.

The fabless concept was a big hit; fabless companies no longer had to pay for equipment depreciation, idle production lines, irregular production schedules, etc. resulting in many other semiconductor companies following on their footsteps. Such success even led to the birth of TSMC, the first “pure-play” foundry in 1987. TSMC, being a pure-play foundry back then, only manufactured and sold wafers—it had no design capability whatsoever.

New relationships rose between fabless companies and foundries/IDMs. A long-term relationship between a fabless company and a foundry had to be built upon mutual trust, and must be mutually beneficial to each other. The fabless company benefits by acquiring access to the most modern fabrication process minus the hefty capital investments, while the foundry benefits through obtaining a diversified manufacturing capacity over different market segments.

How Did the Fabless Model Change the Semiconductor Industry?

During a semiconductor downturn, an IDM can find itself in trouble with its fab since the cost of a running production line is estimated to be almost the same as an idle one. But a fabless company with an urgent need to bring a product to market can come to its rescue.

This is exactly what Chip and Technologies did for Hitachi. C&T had to deliver a chipset when the PC business was booming, so it had to deliver it fast. Hitachi had lots of available fab resources at the time and was in dire need of business as well. Given the law of supply and demand, things ended up with C&T fabricating its product at exceptionally low prices from Hitachi. It was a better choice than not having any customer consequently accumulating expenses from an unused resource.

ASIC companies once dominated the electronics industry because one can overcharge on uncontested IP. This changed, too, when know-how on chip design became publicized and the fabless model emerged. With pure-play foundries, systems companies in the front end had a way to fully skip pure-play ASIC companies. The whole design can be laid out and the only thing needed for tape-out is a foundry like TSMC (which is also known as customer-owned-tooling).

Redesigning a chip is a must due to incompatible processes when shifting between ASIC companies, but not necessary when shifting foundries. Given such lofty advantages, pure-play ASICs were driven to extinction. Today, systems companies, with the help of design service companies, now commonly implement application-specific functions on FPGAs.

Perhaps the fabless model wouldn’t be as successful as it is now without the support of EDA. The key enablers provided by EDA were software that covered the entire semiconductor design flow, including verification, as well as a plethora of IP libraries. These complemented the needs of fabless companies so much so that some software had licensing prices surpassing hardware-automation cost by hundreds of times over due to high demand (something that wasn’t thought possible in the past because the scenario was topsy-turvy—hardware was more expensive than software).

Companies that cater to this kind of EDA, like Mentor Graphics, Synopsys, and Cadence Design Systems, profited a lot. They also didn’t just rely on profit, but spurred growth through acquisitions of promising EDA startups, thus keeping ahead of competition and making it quite difficult for today’s competitors to keep up. As for IP, ARM and Imagination Technologies have dominated this field of EDA, developing architectures of processors and graphics technologies of visual interfaces in products we use and love (i.e., smartphones and tablets, respectively).

What Future does a Fabless Industry Bring?

Perhaps the need for the fabless model is becoming more crucial than ever, as modern trends in technology demand every segment of the semiconductor industry become better and more efficient at its craft. EDA, IP, and fabless companies, as well as foundries and IDMs, need to synergize and work hand-in-hand to open new frontiers for development and innovation.

As foundries implement fabrication processes that approach the atomic level, EDA companies face the challenge of developing their current products to work with these ever changing processes. One example of continuing dynamic improvement in EDA would be the replacement of Cadence’s Diva and Dracula with Mentor’s Calibre physical verification software.

Taking a closer look at the fabless solution, maybe we could clone the gist of the model and apply it to other applicable areas. Segmentation of a process and identifying which particular part would be better off developing as an individual entity is, in my opinion, a good way to adopt what we have learned. Can you think of any areas where such an approach would be remunerative?

Looking for parts? Go to SourceESB.

Discuss this Blog Entry 5

on Jun 20, 2016

although i don't entirely agree i can see what you are getting at.

on Jul 9, 2016

on Aug 14, 2016

Everyday every where something new happening, new inventions reveals. I wish your success in your field of expertise. I am a educationist write poems,articles,essays. Some times I get help from for new ideas for my topics and thesis.

on Oct 3, 2016

and informative post. thanks to share with us.

Please or Register to post comments.

What's Guest blogs?

Bloggers from the industry discuss industry topics

Commentaries and Blogs
Guest Blogs
Jan 26, 2017

An Amateur’s View on the P2 (Part 2): Slew Rate and the Oscillator 3

Justin Mamaradlo takes a further look into the P2 op amp and how it functions, analyzing the oscillation and slew-rate characteristics of the venerable component....More
Jul 15, 2016

Simple Yet Effective ESD Testing Methods for Higher Reliability 11

There are multiple ways to test for electrostatic discharge, ranging from implementing a human-body or machine model to....using a balloon and a comb?...More
Apr 8, 2016

Confabbing on the Fabless Fad 5

High capital and maintenance costs, and EDA advances along with abstractions to deal with chip complexity, have been leading contributors to the fabless migration....More

Sponsored Introduction Continue on to (or wait seconds) ×