FPGAs Get A Performance/Reliability Lift From The Bumps

Recent trends in high-density interconnects have led to the use of copper pillar solder bumps for packaging processes because they provide a fixed stand-off that is independent of pitch


According to Altera it will be the first company to use fine-pitch copper, bump-based packaging technology for commercial purposes. The technology, patented by the Taiwan Semiconductor Manufacturing Company (TSMC), will be deployed in Altera’s 20-nm Arria 10 FPGAs and SoCs.

What makes this fine-pitch version of copper bumping better than the standard stuff? Predictably, Altera says it provides superior quality and reliability. If so, how?

There are some well-documented, practical, and essential design elements relating to high-performance FPGAs. Recent trends in high-density interconnects have led to the use of copper pillar solder bumps (CPBs) for packaging processes because they provide a fixed stand-off that is independent of pitch. This is important, as most high-end products are under-filled and a smaller standoff may cause problems in getting the under-fill adhesive to adequately flow under the die.

Numerous specific benefits are possible with fine-pitch flip-chip manufacturing with copper pillar bumps. They include low-cost, enhanced electro-migration performance, availability of fully developed finite element models to optimize chip package interactions, and their lead-free makeup.

Not only does this technology create the very high bump counts needed for high-performance FPGAs, it also improves bump joint fatigue life and lowers stress on the ELK (Extra Low-K) layers.

Not surprisingly, TSMC’s technology is expected bring higher quality and greater reliability to Arria 10 devices over standard copper bumping solutions because of the fine-pitch design element.

Coolly Efficient

Copper pillar solder bumps, also called thermal bumps, maintain thermoelectric properties that can create a voltage when each side exhibits a different temperature. That brings the design advantage of cooling: Thermoelectric cooling occurs when a current passes through the bump. The bump pulls heat from one side of the device and transfers it to the other; the direction of heating and cooling is determined by the direction of current flow.

A further advantage of TSMC’s fine-pitch copper-bump-based packaging is its scalability, which suits products with large die size and small bump pitch. It includes a design-for-manufacturing/design-for-reliability (DFM/DFR) implementation that can adjust package design and structure for wider assembly process windows. According to TSMC, its technology has demonstrated better than 99.8% production-level assembly yields.

TSMC says it will manufacture 8.0 million wafers this year, including production from three advanced 12-inch facilities, four 8-inch fabs, and one 6-inch fab.

Another First

In another announcement, Altera also claims to have changed the game when it comes to FPGA floating-point DSP performance. The firm says it’s the first programmable logic company to integrate hardened IEEE 754-compliant, floating-point operators in an FPGA. These DSP blocks are integrated in Altera’s 20-nm Arria 10 FPGAs and SoCs.

Design-wise this becomes an important advance because integrated hardened floating-point DSP blocks, combined with an advanced high-level tool flow, enable computationally intensive applications. The DSP blocks are based on a variable precision DSP architecture, which eliminates nearly all of the logic usage required for existing FPGA floating-point computations. 

Please or Register to post comments.

What's London Calling?

Blogs on the electronics industry


Paul Whytock

Paul Whytock is European Editor for Penton Media's Electronics Division. From his base in London, England, he covers press conferences and industry events throughout the EU for Penton...
Commentaries and Blogs
Guest Blogs
Jan 26, 2017

An Amateur’s View on the P2 (Part 2): Slew Rate and the Oscillator 1

Justin Mamaradlo takes a further look into the P2 op amp and how it functions, analyzing the oscillation and slew-rate characteristics of the venerable component....More
Jul 15, 2016

Simple Yet Effective ESD Testing Methods for Higher Reliability 7

There are multiple ways to test for electrostatic discharge, ranging from implementing a human-body or machine model to....using a balloon and a comb?...More
Apr 8, 2016

Confabbing on the Fabless Fad 5

High capital and maintenance costs, and EDA advances along with abstractions to deal with chip complexity, have been leading contributors to the fabless migration....More

Sponsored Introduction Continue on to (or wait seconds) ×