4-ns Clock-To-Out Speed Primes FPGA For 66-MHz PCI Designs

The newest member of Actel's SX family of field-programmable gate arrays (FPGAs) is the 32,000-gate A54SX32. With 4-ns clock-to-out speeds and a 320-MHz maximum clock rate, the device is a candidate for high-performance applications ranging from Gigabit Ethernet to 66-MHz, fully compliant PCI designs.The FPGA enables designers to integrate multiple, high-performance complex programmable logic devices (CPLDs) into a single chip. The result: reductions in power consumption, savings in board space, and slashed costs. Potential applications for the A54SX32 FPGA include networking, telecomm products, data acquisition systems,instrumentation, medical electronics, and high-speed computer peripherals. The chip is the third device in the SX family, following on the heels of the 16,000-gate A54SX16 and 8000-gate A54SX08 announced earlier this year.A number of architectural features are what's behind the A54SX32 chip's performance. For one, there's a hard-wired clock with a maximum rate of 320 MHz. Fast I/Os with a 4-ns clock-to-out rating and input setup times of under 0.6 ns also contribute, as do abundant local interconnects (direct connect 0.1 ns, fast connect 0.4 ns). There's also a new low-impedance metal-to-metal antifuse. All told, the combination enables the device to exceed CPLD performance, it's claimed. For example, a 32-bit-wide decode function takes just 7.7 ns pin-to-pin. All SX devices offer full pin compatibility within the family. They also provide mixed 5V/3.3V support with 3.3V output drive and 5V-tolerant inputs.The ability to achieve full device utilization enables designers of FPGAs to reduce die area, cost and design time. The company's Actel Designer software provides 100% place-and-route capability, and its Silicon Explorer makes debugging easy, it's claimed. Samples are available now.