The adage "divide and conquer" has as much validity in the high-speed data communications market as it does in combat. Today's electronic battlefields substitute buses for warriors and backplanes for territory in the quest to move more data faster. Designers at Rambus Inc., Mountain View, Calif., have put their own spin on the saying.
Several other companies have divided the physical bus into smaller, high-speed serial streams. But Rambus has split the voltage level of the signal into four levels instead of two. Proper sensing allows the signals to transfer two bits of data on every rising and falling edge. The method effectively doubles the data-transmission bandwidth without increasing the clock rate.
This approach is known as the quad Rambus signalling link (QRSL). It employs a coding scheme very similar in some ways to the double-density storage technique adopted by other companies to craft high-density flash memories. Instead of just using the basic 0 and 1 levels, designers added two more reference voltages to divide the signal swing into four segments. These segments then can be used to represent two data bits.
By using a grey-scale coding scheme that keeps the bit transitions to just one per signal level, switching power is held to a minimum. Consequently, the basic Rambus data-transfer speed is 800 Mtransfers/s with a 400-MHz clock rate. With QRSL, the effective data-transfer rate becomes 1600 Mtransfers/s, or 3.2 Gbytes/s when a 16-bit interface is used. A 64-bit bus can use QRSL to deliver a 12.8-Gbyte/s data bandwidth.
To improve the data bandwidth, Rambus developed new transmitter and receiver circuits that are associated with each I/O pin. These circuits perform the multilevel signalling and detection on a multidrop bus, thanks to some novel technology produced by the company.
The receive portion uses an integrating receiver instead of a sampling receiver. The area (voltage times time) under the signal region of interest is measured, whereas the standard sampling approach only uses a single sample (see the figure, a). Although the integrating receiver adds a delay of about 25% of a clock cycle (about 500 ps), an improved data path design in the rest of the memory chip compensates for the delay.
As a result, QRSL offers enhanced noise rejection. This is critical when using smaller voltage levels to distinguish between data values. Improvements to the circuits in the transmitter permit individual calibration of three output current levels to ensure accurate and consistent levels (see the figure, b).
Initially, designers expect to deploy QRSL-based devices on circuit boards for chip-to-chip data transfers between multiple memory chips and the host control interface. The scheme can handle pc-board traces of up to about 5 in. This will give designers better control over the loading and signal integrity of the data signals.
Companies will be able to produce modules using the QRSL interface once the technology matures. After that, manufacturers will be able to implement large-scale memory systems. A test system was constructed by the company, and a two-drop multilevel implementation was compared to a 32-drop dual-voltage subsystem. The QRSL system's Shmoo-plot performance was comparable to that of the dual-level system, proving the feasibility of the scheme.
For more information, check out www.rambus.com.