By combining the functions of a control-plane processor and a network processor, the Octeon processor can take on data traffic at rates of up to 10 Gbits/s. Developed by Cavium Networks, this processor performs content, security, compression/decompression, and TCP/IP offload functions thanks to an architecture that blends as many as 16 MIPS64 64-bit processor cores, two serial-packet-interface processors (SPI 4.2), and specialized coprocessors (see the figure).
The Octeon handles data traffic in layers 3 to 7 by supporting firewalls, virtual private networks, and anti-virus and anti-spam features to deter network threats. It supports a wide range of applications, such as HTTP, XML, VoIP, Mail, Chat, MP3, and MPEG. To deal with all of these requirements, the Octeon employs a highly programmable architecture and dedicated on-chip accelerators for TCP/IP, Security (3DES, AES, RAS, DH, Hashing), regular expression handling, and compression/decompression (GZIP).
Each dual-issue 64-bit integer core includes a 32-kbyte instruction cache and an 8-kbyte data cache. All 64-bit cores share a 1-Mbyte, eight-way, set-associative L2 cache with error-checking and correction to ensure data integrity. To feed data into the chip, an on-board double-data-rate (DDR) SDRAM interface (either 72 or 144 bits wide) performs data transfers at up to 800 MHz from external DDR I or DDR II memory. In aggregate, the MIPS processors execute 19.2 billion instructions/s when the chip operates from a 600-MHz clock.
The multiple cores on the Octeon can run a full operating system (such as a multiprocessor Linus OS) and/or run tuned data-plane-like code. Task allocation of the cores is determined by the programmer. The dual-packet I/O processors support IPv4 and IPv6 traffic at up to 10 Gbits/s and perform L2-L4 parsing, error checks, tagging, queuing, and work scheduling.
Dedicated engines packed into the regular-expression processor block accelerate pattern and signature match operations—necessary for anti-virus, IDS, and content processing applications—up to 4 Gbits/s. The dedicated TCP acceleration engine performs hardware-based packet synchronization, timer support, and buffer management to deliver 10 Gbits/s of full TCP termination. And, the compression/decompression processor handles GZIP, PKZIP, and other compression protocols to deliver compressed data at up to 4 Gbits/s.
Four versions of the Octeon processor, with two, four, eight, or 16 MIPS64 cores, will be available. This will let designers better match performance and cost. Versions with two or four MIPS64 cores will use a 72-bit memory interface and come in a 709-lead package. The eight- and 16-core versions pack a 144-bit wide memory interface and come in a 1500-lead package.
In 10,000-unit lots, the Octeon processors will cost from $125 to $750 each.
Cavium Networks Inc.www.cavium.com