PCI-To-Fibre-Channel Controller IC Boasts Dual 2-Gbaud Links

The system performance of workstations, servers, and storage-area networks should be greatly enhanced with a new PCI-to-Fibre-Channel protocol controller. Dubbed the Symbios SYMFC929, this dual-channel controller works with both 32- and 64-bit PCI systems with bus speeds of 33 or 66 MHz, respectively. Each channel has a data rate of 2 Gbaud.

The dual-channel architecture effectively doubles I/O performance by increasing throughput, improving efficiency, and employing a scalable architecture. This combination adds to system performance without changing the storage infrastructure.

A product of LSI Logic, the SYMFC929 controller supports all major Fibre Channel topologies with full-duplex communications on both channels. Integrated onto the device is the company's GigaBlaze 2-Gbaud Fibre Channel serial link.

According to the company, this is the first chip to support Fibre Channel protocol (FCP) and Internet protocol (IP) intermixed on both channels at the same time. When necessary, designers have the flexibility to mix or offload all IP traffic from the FCP storage traffic.

The 2-Gbaud channels can auto-negotiate independently. That means that they can automatically switch between 1-Gbaud and 2-Gbaud data rates. With this feature, a designer can separate legacy and next-generation devices for maximum flexibility in a system configuration.

The controller eliminates the need for a PCI bridge, second single-channel Fibre Channel controller, and associated memory and support devices typically found in dual-channel designs. This saves circuit-board real estate and lowers power consumption. Suited for both host and embedded-system designs, the device lets OEMs and system integrators take full advantage of today's dual-channel drive storage devices. They can then implement very cost-efficient storage systems.

To control all system-interface and dual-channel functions, the SYMFC929 uses a custom ARM RISC processor. The host CPU is thus freed up for other processing activity, improving overall I/O performance (see the figure). The RISC processor and associated firmware can manage I/O signals from start to finish without host intervention.

A 32-bit memory controller gives access to 32-bit synchronous SRAM and flash memory. It supports both interleaved and non-interleaved configurations up to a maximum of 2 Mbytes of synchronous SRAM. A general-purpose memory-expansion bus provides for up to 1 Mbyte of flash memory.

The PCI interface implements the PCI buses as noted above. It can handle a dual-address cycle (DAC), PCI power management, subsystem vendor ID, and vendor product data (VPD). In addition, the interface supports extended-access cycles, such as MRL, MRM, MWI.

The SYMFC929 contains an integrated link controller, which is FC-AL-2 r7.0-compliant, to monitor the link state and strictly adhere to the Loop Port State Machine. This ensures maximum system interoperability. According to the company, the chip passes "SAN Mark" interoperability testing, as well as additional extensive link tests performed at Medusa Labs.

For diagnostic purposes, the device can perform a simplified bit-error-rate (BER) test on the link. In this special test mode, the controller can transmit and verify pre-programmed data patterns for link evaluation. This provides a cost-effective tool to the system administrator for simple debug situations.

To complement the SYMFC929 and the SYM44929LH/LO host-adapter boards, the company offers a complete software suite. Operating systems supported include Windows NT, Windows 2000, Netware, Unixware, Linux (Red Hat support), and Solaris.

As you may know, LSI Logic has developed standardized software support, known as the Message Passing Interface (MPI). This interface, originally implemented for the SYMFC909 single-channel PCI-to-Fibre Channel host adapter, is incorporated into the SYMFC929 dual-channel controller.

LSI Logic Corp., 1551 McCarthy Blvd., Milpitas, CA 95035; (408) 433-8000; www.lsilogic.com