Reconfigurable Architecture Targets Military Sensor Systems

July 19, 2007

Raytheon developed its MONARCH (Morphable Networked MicroArchitecture) architecture and chip under a Defense Advanced Research Project Agency (DARPA) polymorphous computing architecture contract from the U.S. Air Force Research Laboratory (see the

William G. Wong

It is designed to outperform existing quad-core processors by a factor of 10 in environments that MONARCH was specifically designed for—in this case, processing large amounts of sensor data for applications such as video and radar analysis.

The chip's field-programmable computer array (FPCA) operates in one of three modes: MIMD, SIMD, and Stream. The various hardware clusters are configured to support the current operating mode. A high-speed ring delivers data between compute, storage, and interfaces at 43 Mbytes/s.

The MIMD configuration lets independent applications run on the RISC processors. The SIMD operates the processors in an Altivec-like vector mode. These modes typically are programmed using C. The Stream architecture takes advantage of the crossbar fabric in the FPCA but tends to be more difficult to program.

Multiple chips can be linked together using the differential inter-FPCA links (DIFLs). Four chips can easily fit onto a single VME board. Serial RapidIO provides access to off-chip peripherals and services. The platform suits rugged and space environments.

Raytheon
www.raytheon.com

MONARCH (Morphable Networked Micro-Architecture)
Architecture: reconfigurable system that operates in one of three modes
Memory: 12 Mbytes of on-chip embedded
DRAM; two DDR2 interfaces supporting up to 4 Gbytes/interface at 5.33 Gbytes/s
Clock: 333 MHz (initial version)
Process technology: 90-nm bulk CMOS
Interface: 16 port, bidirectional Inter-PCA (Polymorphous Computing Architecture) links; 12 for intra-board communication, four for inter-board communication; 1.3 bytes/s/direction for a total of 42.67 Gbytes/s/chip
Peripheral interface: two 4x Serial RapidIO interfaces with a bandwidth of 1.25 Gbytes/s
FPCA performance: 3 to 6 GFLOPS/W
Power: about 20 W max

FPCA Modes Of Operation
MIMD: six 32-bit RISC SMP processors; no cache; no register files; all code and data use embedded DRAM
SIMD: seven vector processors; easier to program than Stream mode; Altivec-like architecture
Stream: 96 ALUs and multipliers connected by a crossbar fabric