Stunning Advances To Captivate ISSCC Attendees

A truckload of the latest innovations awaits designers attending next month's IEEE International Solid State Circuits Conference, Feb. 7-10 at the San Francisco Marriott. In fact, the 2005 ISSCC will offer the conference's largest technical program in its over-25-year history.

Highlighted developments will range from nanotechnology to billion-plus transistor CPUs and 8-Gbit flash memories. Three plenary sessions that all focus on the impact of nanotechnology on different aspects of the industry will officially kick off the conference.

Then, digital designers should expect a virtual feast of developments. A bevy of papers will detail a dual-core Itanium processor from Intel and Hewlett-Packard. With 1.72 billion transistors, the chip packs the largest cache to date on a CPU—over 26 Mbytes (paper 10.1). In the same session, Sun Microsystems will describe a dual-core SPARC V9 processor that clocks at 1.8 GHz (paper 10.3).

Developments in NAND, DRAM, and SRAM are sure to create a stir. A pair of presentations in session 2 will describe the industry's first 8-Gbit flash memory chips (papers 2.1 and 2.2). Toshiba and SanDisk used 70-nm design rules to craft a chip that can program its cells at up to 6 Mbytes/s. Also, Samsung will discuss a 63-nm design that can program at 4.4 Mbytes/s while offering a high read throughput of 23 Mbytes/s. Another paper by Samsung will shed light on a 64-Mbit nonvolatile memory based on phase-change materials (paper 2.3).

In the DRAM session, Toshiba will describe the first capacitor-less DRAM based on a floating-body cell and silicon-on-insulator technology (paper 25.1). In paper 25.6, Samsung designers will unveil a 2-Gbit second-generation double-data-rate DRAM that can transfer data at 800 Mbits/s/pin.

High-speed interfaces and backplane transceivers will take center stage as designers improve the data bandwidth between chips or boards on a motherboard or backplane. Sessions 3, 8, 18, 22, and 28 will focus on data-transfer, clocking, and high-speed serial I/O schemes.

Many presentations will venture into wired and wireless communications. Sessions 5, 11, 14, and 23 will look at wireless local-area networks, Ultra-Wideband, and other schemes. Sessions 17, 21, and 29 will examine developments in basic RF techniques. A session on baseband processing and another on optical communications (sessions 24 and 12, respectively) will round out the main comm discussions.

Analog and mixed-signal designs will be the focus of sessions 4, 6, 9, 15, and 27. Session 4 will feature several papers that detail novel semiconductor chips with ion channels, nerve cells, and brain tissue developed by the Max Planck Institute for Biochemistry, Munich, Germany (paper 4.1). An analog bionic ear processor developed at MIT will be the subject of paper 4.2. Paper 4.3 will discuss a microfluidic hybrid microsystem for the 2D magnetic manipulation of individual biological cells, developed jointly by Harvard University and the Harvard Medical School.

Several other specialized sessions on image sensors, mass storage, non-imaging sensor technology, and advanced array structures will flesh out the menu (sessions 19, 31, 13, and 32, respectively).