Leuven, Belgium, and California, USA: Synopsys and Imec, the Belgian nanoelectronics research centre, will collaborate to use Synopsys TCAD (Technology Computer-Aided Design) finite-element method tools for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs). The collaboration is expected to accelerate the development of 3D stacked IC technologies.
While considered an emerging technology, 3D stacked ICs complement conventional transistor scaling. They also enable multiple chips to be stacked and integrated into a single package.
This technology reduces form factor and power consumption. Additionally, it increases bandwidth of inter-chip communication by minimizing connections through the circuit board with high parasitic capacitance. As with other innovative technologies, 3D stacked ICs introduce a number of issues that can potentially affect reliability and performance.
The collaborative research to address these issues will take place at Imec, where silicon wafers with test structures will be manufactured and tested. Synopsys TCAD tools will be used to model the TSVs in the chip stacks to optimize 3D stacked IC performance and reliability.