In his latest "Verification Veritas" column, EVE's Lauro Rizzatti explores the intersection of multicore-SoC design and emulation.
Don't let physical stresses or thermal mismatches derail your chip/package/board co-design efforts! TI's Darvin Edwards shows you how to work through some common co-design pitfalls.
Cadence Design Systems' Chi-Ping Hsu muses about what it will take to achieve acceptable yields at the 20-nm process node, when double patterning lithography becomes a reality.
Calibre Pattern Matching is an extension to SVRF that simplifies complex rule checks required for advanced IC processes. This white paper discusses the conditions that have created the need for pattern matching techniques, the identification and creation of patterns, the Calibre Pattern Matching process, and the benefits derived from its use. From Mentor Graphics. >> Download now.
Get expertise in the power for processors and FPGAs arena - visit the Power for Processors microsite from Texas Instruments and Electronic Design. Check out:
By David Maliniak, February 07, 2012
Accurate thermal management depends on accurate simulation models. Mentor Graphics' thermal characterization and analysis methodology builds thermal models of IC packages and LEDs for use in FloTHERM thermal simulations.
By David Maliniak, February 02, 2012
Enhancements to CoventorWare, a MEMS design and simulation tool, enable creation of more efficient 3D simulation meshes.
By Staff, January 26, 2012
Mentor Graphics has expanded its displaced worker program to provide training to EDA workers in Europe who are unemployed.
By Staff, January 17, 2012
The company is seeking to recruit 30 skilled verification specialists for the operation.
David Maliniak
Presented By Maxim
Presented By Datatronics
EDA / Michael White
EDA / Lauro Rizzatti
EDA / Richard Ho