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  1. What's The Difference Between IPv4 and IPv6
  2. What’s the Difference Between 3G and 4G Cellular Systems?
  3. Behind the Scenes at CES 2012
  4. Understanding Modern Digital Modulation Techniques
  5. Does Wi-Fi Put Danger In Your Pocket?
  6. What’s All This Spicey Stuff, Anyhow? (Part I)
  7. Tools Enable More Analog Innovation In 2012
  8. Automotive ICs Keep Catastrophes At Bay
  9. High-Power LED Modules Demand Specialized Electrical Test Tools and Techniques
  10. Rediscover The Truly Tunable Hall Network

  • When Heat Is On, Thermal Characterization Keeps Things Cool

    By David Maliniak, February 07, 2012

    Accurate thermal management depends on accurate simulation models. Mentor Graphics' thermal characterization and analysis methodology builds thermal models of IC packages and LEDs for use in FloTHERM thermal simulations.

  • Formal Techniques for Protocol Verification: A Case Study On Verifying the ARM ACE Protocol

    By Rajeev Ranjan, January 11, 2012

    More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol.

  • Co-Design Reliability Relies On Sound Validation Approaches

    By Darvin Edwards, January 06, 2012

    Nowhere does "garbage in, garbage out" apply more than to models and simulation. TI's Darvin Edwards discusses how to ensure that you're validating IC-package co-design models properly against physical measurements.

  • Virtual Platforms And TLMs Going Mainstream

    By David Maliniak, December 27, 2011

    EDA has begun to grow, and nothing within EDA is growing faster than the electronic system-level (ESL) segment. Here's what you can look for in ESL tools and methodologies in 2012.

  • Open Web Portal Traffics In Transaction-Level Models

    By David Maliniak, December 27, 2011

    An open web portal called TLMCentral aspires to be a one-stop shop for all things related to transaction-level modeling (TLMs).

  • Social Media And Streaming Video Give EDA Cause For Optimism

    By Lauro Rizzatti, December 27, 2011

    Social media begets traffic, traffic begets bandwidth, and bandwidth, or the lack thereof, begets consternation. EVE's Lauro Rizzatti connects the dots between Facebook, EDA, and a new generation of network infrastructure.

  • The Next Level Of Design Entry—Will 2012 Bring Us There?

    By Frank Schirrmeister , December 05, 2011

    Cadence's Frank Schirrmeister explains how the industry is edging its way toward adoption of virtual platforms and transaction-level modeling with hybrid TLM/RTL approaches and ever-larger FPGAs.

  • Multicore SoCs Make Emulation Mandatory

    By Lauro Rizzatti, November 10, 2011

    In his latest "Verification Veritas" column, EVE's Lauro Rizzatti explores the intersection of multicore-SoC design and emulation.

  • Dealing With The Pains Of Technology Adoption

    By Frank Schirrmeister , September 26, 2011

    How is Netflix like a system-level design methodology? Both can be about alleviating pain; Frank Schirrmeister connects the dots in his latest From Systems to Silicon column.

  • Is An Emulation Hockey Stick Coming?

    By Lauro Rizzatti, September 16, 2011

    SoCs are no longer part of the system; they are the system. The explosion in SoC operating modes points toward a verification crunch. Emulation is a technology whose time in the spotlight may have finally arrived. EVE's Lauro Rizzatti explains why.

  • Use Thermal Analysis And Other Types Of Simulation To Craft A “Cool” Design

    By Byron Blackmore, September 16, 2011

    Thermal analysis is critical in determining potential failure mechanisms in ICs, packages, and boards. What is often less well understood is how thermal analysis ties in with electrical and electromagnetic analyses. This article digs into those dependencies.

  • Maximizing Hierarchical Design Throughput for Today’s Large Designs

    By Steve Kister, August 15, 2011

    Hierarchical design methodologies that introduce concurrency into the design flow are the answer to burgeoning circuit complexity. Synopsys's Steve Kister discusses various challenges to design exploration and design planning in a hierarchical flow for large SoCs.

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