Electronic Design Electronic Design Europe Microwaves & RF Power Electronics Technology Source ESB Mobile Dev & Design Engineering TV
View this week's entry ad Subscribe Contact Register Sign In
Twitter Logo Facebook logo RSS Feed Logo Newsletter Logo
  • Channels
Part Inventory
Go
 
powered by:

 
  • Quick Poll
What Social Networking site do you use the most?



VOTE VIEW RESULTS
Previous Polls

Top Tags in IC Physical Design And Verification Tools

Videos in EDA

Top Articles Most Emailed Most Commented
 

  1. What's The Difference Between IPv4 and IPv6
  2. What’s the Difference Between 3G and 4G Cellular Systems?
  3. Behind the Scenes at CES 2012
  4. Understanding Modern Digital Modulation Techniques
  5. Does Wi-Fi Put Danger In Your Pocket?
  6. What’s All This Spicey Stuff, Anyhow? (Part I)
  7. Tools Enable More Analog Innovation In 2012
  8. Automotive ICs Keep Catastrophes At Bay
  9. High-Power LED Modules Demand Specialized Electrical Test Tools and Techniques
  10. Rediscover The Truly Tunable Hall Network

  • MEMS Design Tool Continues To Evolve

    By David Maliniak, February 02, 2012

    Enhancements to CoventorWare, a MEMS design and simulation tool, enable creation of more efficient 3D simulation meshes.

  • While 28 nm Is Still Teething, 20 nm Will Be A Barrel-o-Monkeys

    By Michael White, December 27, 2011

    Even as 28-nm production is ironed out, 20 nm is coming on, bringing with it double-patterning lithography and changes to design-rule checking and other verification parameters. Mentor Graphics' Michael White has the details in this column.

  • Data Management For EDA Apps Sees Gains In 2011

    By David Maliniak, November 29, 2011

    Sometimes a tool's management of the data it generates is as important as the data itself. This year's Best in EDA winners, Mentor Graphics' Calibre RealTime and Altium's Altium Designer 10, both make their mark through innovative data-management schemes.

  • Does Double Patterning Mean The End Of The World?

    By Michael White, November 28, 2011

    Double patterning litho technology is the order of the day at the 20-nm node, but you need not fear it: Mentor Graphics' Michael White takes you through the basics and some of what you need to do to prepare for your next-generation chip design cycle.

  • Common Ground: Seeking Pin Assignment Balance in FPGA-Based Boards

    By Bruce Riggins, November 21, 2011

    Integrating these ever-more complicated devices into their host PCBs has proven to be extraordinarily challenging. With better FPGA design-in tools that communicate in several languages, FPGA design-in can be a faster, less frustrating endeavor.

  • Cultivate A Model Of Success In Co-Design

    By Darvin Edwards, November 10, 2011

    Don't let physical stresses or thermal mismatches derail your chip/package/board co-design efforts! TI's Darvin Edwards shows you how to work through some common co-design pitfalls.

  • How To Succeed At 20 nm

    By Chi-Ping Hsu, November 10, 2011

    Cadence Design Systems' Chi-Ping Hsu muses about what it will take to achieve acceptable yields at the 20-nm process node, when double patterning lithography becomes a reality.

  • Maximizing Hierarchical Design Throughput for Today’s Large Designs

    By Steve Kister, August 15, 2011

    Hierarchical design methodologies that introduce concurrency into the design flow are the answer to burgeoning circuit complexity. Synopsys's Steve Kister discusses various challenges to design exploration and design planning in a hierarchical flow for large SoCs.

  • What Does Design Rule Signoff Really Mean—And When Should I Care?

    By Michael White, August 15, 2011

    It would be nice if process rule decks settled down quickly, but they don't; in fact, often, they never do. Mentor Graphics's Michael White discusses how best to deal with design-rule signoff for leading-edge processes.

  • Programmed Splitting Of Full-Chip Calibre DRC/ERC Errors Into Sub-Block Space

    By Arya Raychaudhuri, August 09, 2011

    Ever wish you could run design-rule and electrical-rule checking in Calibre once at full-chip level and break them down into the sub-block level? This article will show you how to do that.

  • Realizing the Promise of Electrically-Aware Custom IC Design

    By David White, August 09, 2011

    How does one achieve electrically aware custom IC design? For one thing, through real-time, in-design parasitic extraction and analysis. Cadence's David White and Michael McSherry explain.

  • Are We Ready For Physical Verification Standards?

    By Michael White, June 30, 2011

    In his latest Silicon Edge column, Mentor Graphics' Michael White discusses the OpenDFM and iDRC standards for DRC syntax and what it will take to get them more widely adopted.

Sponsored Links