Programmable Clock Improves Gigabit Network Performance

June 25, 2009
As network speeds increase, the jitter performance of the timing clock becomes a major design factor. The best solution is to start with a quality clock with minimum jitter. Cypress Semiconductor’s FleXO family of programmable high-performance clock gener

As network speeds increase, the jitter performance of the timing clock becomes a major design factor. The best solution is to start with a quality clock with minimum jitter. Cypress Semiconductor’s FleXO family of programmable high-performance clock generators deliver ultra-low phase jitter as low as 0.6 ps typical from 12 kHz to 20 MHz.

This performance exceeds the requirements of demanding high-speed serial interface network standards such as 10 Gigabit Ethernet, 10 Gigabit Fibre Channel, PCI Express, and Serial Advanced Technology Attachment (SATA). The flexible clocks can be instantly programmed at the factory or in the field to any frequency from 50 to 650 MHz. Their programmability speeds development and simplifies testing for improved manufacturing quality.

The devices’ programmable phase-locked loop (PLL) can be used in integer or fractional-N mode to synthesize and tightly control the frequency of ultra-low-noise clock signals using a standard low-cost crystal input. They provide an alternative to surface acoustic wave (SAW) oscillators and overtone crystal oscillators (XOs). The family is ideal for switches and routers, 3G wireless basestations, fiber-to-the-home (FTTH) hubs, enterprise hard-disk drives, test equipment, professional video equipment, and any system requiring high-performance clocks.

The family leverages Cypress’ patented programmable clock technology to instantly generate any frequency from 50 to 650 MHz, including non-standard frequencies often required to optimize performance of an FPGA or ASIC. Designers can adjust the output frequency of a FleXO clock via simple pin selection or I2C programming to allow usage of a single device across a family of hardware platforms.

The clock generators also support frequency margining, which enables designers to vary clock frequency with 0.2-ppm precision to test system robustness across potential frequency fluctuations. The FleXO family is available in a broad array of synthesizer, voltage-controlled oscillator (VCO), crystal-outside (XO), crystal-inside XO, and voltage-controlled XO (VCXO) options to support a variety of applications.

Currently in production in multiple configurations, the FleXO clock generators are available in an eight-pin thin-shrink small-outline package (TSSOP), a 16-pin TSSOP, and a six-pin leadless chip carrier (LCC) package. The CY3675-CLKMAKER1 CyClockMaker Programming Kit is available for $160, and the CY3675-LCC6A FleXO Socket Adapter is available for $57.

Cypress Semiconductor Corp.

www.cypress.com

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