State diagrams are a simple, yet elegant way to model complex systems, regardless of the implementation. Most state machines are designed to be synchronous. However, there are many applications that aren't well suited to a state machine that's limited to changing states on the edge of a clock. Such systems may require state transitions on both edges of a clock, or match dissimilar interfaces where state transitions must occur when control signals change levels.
Asynchronous state machines have many advantages of their synchronous counterparts, but aren't limited to making transitions on a clock edge. One very simple state machine is the common SR latch. It has only two states, and transitions are made in direct response to the Set and Reset inputs without a clock. More complex systems require some precautions. With asynchronous transitions, care must be exercised to ensure that race conditions don't cause non-deterministic behavior. This can be done by encoding the states in a Gray code so that only a single state bit changes for each state transition. If more than one bit were to change, then skew would cause transitions through undesired states, causing glitches, oscillations, or unwanted state transitions. This precludes using a "one shot" implementation more common in FPGAs where each state corresponds to one storage element, because as one element turns off, the other turns on, and decoding glitches would result.
An example of a simple, asynchronous Gray-code state machine is shown (Fig. 1). As seen in the timing diagram (Fig. 2), the application required a Strobe signal (DSTROBE) to be generated by transitions of two different control signals. The first strobe had to be triggered by the first falling edge of the DMA Acknowledge signal (DACK-). All subsequent strobes had to be triggered by the rising edge of the Read Enable Not signal (RE-). The state diagram models this behavior. The Off state is necessary because a transition directly from Wait to Idle would require two bits to change simultaneously. The S0 bit changes first in going to Off, then S1 changes going to Idle. The state storage elements are latches implemented as multiplexers. In a multiplexer rich architecture like an Actel FPGA, this circuit is very efficient.
