Pseudo-random bit sequences (PRBSs) are widely employed in various applications, such as test sources, noise generators, and scrambling and spread-spectrum systems. A common implementation is to employ an n-stage shift register with modulo-2 feedback at m taps to generate a maximum length sequence 2n − 1. These sequences will cycle through all n-bit states with the exception of the all-zero state. Therefore, at power initialization, the shift register will remain in a static condition, because 0 ⊕ 0 = 0, where⊕ denotes the exclusive-OR operator. As a result, additional logic is required to inject at least one logic 1 bit into the shift register at power startup.
In this circuit (see the figure), an additional exclusive-OR gate is connected after the modulo-2 feedback, with C1 and R2 applying the supply turn-on ramp into the feedback loop. This provides sufficient transient signal so that the PRBS generator can self-start at power-up. A shift-register length n of 10 is shown with feedback at stages 3 and 10, providing true and inverted maximal length sequence outputs.
This technique applies an input directly to the feedback loop. Therefore, it's considered more reliable than applying an RC configuration to the shift-register reset input to create a random turn-on state.