The huge undertaking of verifying a system-on-chip (SoC) design has challenged engineers for more than 20 years –– the amount of time spent on it hasn’t varied much from between 50-70% of the entire development cycle. That’s because time-to-market pressures relentlessly increase, as do design sizes. However, verification budgets don’t increase at the same rate, forcing management to use available resources more efficiently...
Register or Sign in below to download the full article in .PDF format, including high resolution graphics and schematics when applicable.