Switching systems continue to be called on to deliver higher packet throughputs and higher quality-of-service levels. Switching circuits controlling the data flow must perform more and more packet analysis and routing functions at wire speeds. Delays associated with performing the analysis can't be tolerated, as many media-rich files the network must now transport are time-dependent.
Developed by Marvell Semiconductor, the Prestera chip set is taking on the challenge of handling data streams at 10 Gbits/s and offering system scalability and high levels of quality-of-service (QoS). It supports layers 2 through 5 of the International Standards Organization's Open Systems Interconnect reference model, multiprotocol label switching (MPLS), and many other advanced features. The Prestera packet processor and supporting chips in the chip set deliver the first switching architecture to simultaneously perform processing for layers 2, 3, and 4, and MPLS network address translation (NAT) and load-balancing at 10-Gbit/s data rates.
In contrast, the best current competitive solutions only perform processing for layer 2 (L2) at 10 Gbits/s, or use highly flexible and programmable network processors that perform L2 through L4 at 2.5 Gbits/s. The chip set also has the flexibility to address the requirements of Enterprise as well as core and metropolitan area networks (MANs). That enables OEMs to address multiterabit architecture scalability versus competitive standalone solutions. Additionally, this solution offers a single software and hardware architecture for 10-Gbit Ethernet, 1-Gbit Ethernet, and Fast Ethernet, letting OEMs address high-end to low-end solutions from multiterabit-class switches and routers to simple desktop switches.
Scaling Back The chip set can be scaled to handle the terabit data flows needed to serve the large MANs and more moderate hundreds of gigabits per second flowing in Enterprise-class systems. The Marvell Prestera switching architecture is broken into a three-chip solution for the typical line card, and another chip that would be used to form the high-level switch fabric.The main chip that handles all packet data is the Prestera packet processor. On this chip, designers at Marvell have implemented all the packet buffering, transmit and receive memories and queuing engines, a flow classifier, packet and protocol processing, a 15-Gbit/s expansion bus, and a 10-Gbit/s media access controller (Fig. 1).
The ingress control pipe is a high-performance multistage pipeline designed to make packet-processing decisions at full wire speed for all incoming packets. Some of the processing and decision making that happens within this block includes layer 2 switching and all 802.1D/Q bridging functions, including support of link aggregation groups per 802.3ad and various 802.1 control protocols, layer-3 IPv4 unicast/multicast forwarding, and multi-field flow classification to classify up past layer 5 at full-wire speed. The results of this classification then affect stages of the pipeline responsible for CoS marking, NAT, filtering, and policy-based routing/switching. The block also performs traffic conditioning, which is responsible for Policing, Re-Marking CoS, Billing, MPLS switching, and a wide variety of security mechanisms that operate at L2, L3, and MPLS.
There will initially be four versions of this chip; two targeted at MAN/core applications for the highest-performance systems, and two targeted at Enterprise-class systems. Each pair of circuits is further differentiated. One version contains a single 10-Gbit port to access the network, while the other contains 10 1-Gbit ports, each capable of 10/100/1000-Mbit/s Ethernet packet switching (the Prestera 98MX630/620 for MAN/core systems, and the 98EX130/120 for Enterprise systems).
On the network side, the packet processor ties into a physical-layer device such as the company's Alaska family of Gigabit Ethernet transceivers. On the other side of the packet processor is a 15-Gbit/s expansion bus and an interface to the Prestera switch-fabric adapter. The Prestera fabric adapter, in turn, ties the line to a high-performance switch fabric using either a CSIX-compatible parallel bus or a serializer/deserializer (SERDES) serial interface.
Although the line card will contain several other circuits, the Alaska family of Gigabit Ethernet Transceivers, the Prestera packet processor, and the Prestera fabric adapter form the basic architecture of the line cards. Depending on which version of the packet processor chip is selected, each line card can provide either one 10-Gbit channel or 10 1-Gbit channels (Fig. 2). Multiple line cards can then be connected to the switch fabric that will be formed using a fourth chip currently in development at Marvell.
From an architectural viewpoint, all four versions of the Marvell Prestera packet processors are similar. However, the MAN/core versions can perform full wire-speed L2 bridging, L3 routing and L2 to L5 advanced traffic classification, filtering, and prioritization. The 98MX620 and 98MX630 also provide powerful MPLS, NAT, and bandwidth provisioning functions. In addition to a rich feature set, the 98MX620 and 98MX630 take advantage of the scalable memory architecture to support millions of IP routes and flows.
The Prestera 98EX120 and 98EX130 focus on the Enterprise market requirements. They offer full wire-speed L2 bridging, L3 routing, and L2 to L5 ad-vanced traffic classification, filtering, and prioritization. But they don't handle MPLS, and they lack traffic metering and billing abilities. Compared to the Prestera MX devices, the Prestera EX packet processors also support smaller IP and flow tables.
Expansion With No Sacrifices The separate 15-Gbit/s expansion port on the Prestera packet processors allows easy connection to the Prestera fabric adapter for stacking systems without using a crossbar. Additionally, in many areas, high reliability is a key requirement to ensure uninterrupted network operation. To that end, Marvell's designers let the chips be used in a dual-ring stacking architecture. This provides redundancy and allows load balancing. Also, the Prestera architecture supports virtual output queues for up to 64 devices (eight per chip).The L3 routing engine lets the chip perform IPv4 forwarding in hardware, execute longest-prefix matches for 32-bit IPv4 addresses, and support IP multicast routing that includes source-based multicast protocols, like PIM-SM/DM and DVMRP. In addition, the routing engine supports 8k IP multicast groups and performs equal-cost and weighted-cost path routing.
One key aspect of the Prestera packet processor is its advanced traffic management and QoS capabilities, which include eight priority queues with three drop precedences and WRED (Weighted Random Early Discard). The traffic scheduling and bandwidth management helps ensure that packets are delivered on time to their final destinations. Advanced traffic policing and application-aware QoS and filtering also are supported by the packet processors to enable service-level agreements (SLAs) and provide network security.
The Prestera 98MX620 and 98MX630 support MPLS for Virtual Private Networks (VPNs) and traffic engineering with four labels. They perform the function either as a label-edge router (LER) by sitting on the edge of the MPLS networks and add tags, or as a label-switch router (LSR) in an MPLS network and switch traffic based on MPLS tags.
Supporting L4 traffic engineering too, the chips provide network address and port translation and can perform L4 switching and load balancing. The packet processors can perform wire-speed L2 switching. Up to 16k MAC addresses are supported, along with up to 8k virtual LAN connections based on the number of MACs, ports, subnets, and protocol. The engine links aggregation and port trunking (802.3ad-compliant) across multiple 1-Gbit ports. Plus, it supports multiple spanning tree-broadcast storm-rate filtering and port mirroring (802.1s-compliant).
To provide the storage necessary for the packets, external double-data-rate DRAMs are used. A 32-bit 66-MHz PCI interface provides a connection to a host management processor that coordinates system operations. Despite the large number of buses and high-speed I/O lines, the chip is housed in a 901-contact thermally enhanced plastic BGA package. However, the chip isn't a power hog, consuming just 4 W.
Providing the physical interface to network, Marvell offers single-, dual-, and quad-port Alaska Gigabit Ethernet transceivers. These transceivers deliver some of the "best-in-class" solutions by providing high-performance, low power dissipation and the smallest form factor package solutions commercially available today. The feature-rich Alaska Gigabit PHYs also include a built-in SERDES, which provides flexibility in the selection of copper or optical interfaces on a per port basis.
For 10-Gbit applications, Marvell's Alaska-X Ethernet transceiver, the 88X2040, is a 10GBASE-X PHY and can also be used as an XGXS (10G extender) to connect to an MSA 50/70 optical module. The 88X2040 10-Gbit PHY contains four 3.125-Gbit/s SERDES channels. Each transceiver channel includes a selectable 8B/10B encoder/decoder. Furthermore, all four channels can operate in lockstep, allowing the chip to comply with the 802.3ae draft specification. Or, the ports can operate independently for backplane or redundant applications.
The transceiver includes the clock and data-recovery circuits as well as the deserialization for the receive path. For the transmit path, the circuit also has pre-emphasis, serialization, and clock-generation logic.
The chip, housed in a 256-contact thin, fine-pitch BGA package, occupies minimal board space and can implement network interfaces or backplane serial communication channels. Implemented in CMOS with 0.15-µm design rules, the quad-channel transceiver consumes the least amount of power of any 10-Gbit transceiver—less than 1 W for the four-channel chip, while delivering the highest throughput. The chip also provides a seamless interface to the optical modules.
The forthcoming fabric adapter and Prestera switch fabric complete the overall Prestera architecture. The fabric adapter chip will permit use of the packet processors in a full-mesh configuration, providing a backbone interconnect fabric by employing an on-chip crossbar and the company's high-performance SERDES ports (Fig. 3). That will also enable stackable switches to connect at multiple gigabit speeds rather than at the half-duplex 1-Gbit/s speeds used by most other systems.
The high-performance Prestera switch-fabric chip, the last piece of the chip set, will form the heart of the Terabit switch fabric. It will allow system expansion beyond a single chassis as bandwidth needs grow.
Price & AvailabilityThe Prestera packet processors, the 98MX620 and the 98EX120, cost $590 and $190, respectively, in 1000-unit quantities. They will be ready for sampling in the first quarter of 2002. The Prestera switch-fabric adapter circuit will be ready for sampling in the second quarter, and the switch-fabric chip will sample in the third quarter. Prices for those chips haven't yet been established. Immediately available is the Alaska X, a four-channel 10-Gbit Ethernet transceiver. It costs $78 each in 1000-unit quantities.Marvell Semiconductor Inc., 2350 Zanker Rd., San Jose, CA 95131; Mike McDonald, (408) 570-4899; www.marvell.com.