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Digital Technical Features

  • MIPS Aptiv Family Brings Consolidation And Raises Performance Bar

    MIPS Aptiv Family Brings Consolidation And Raises Performance Bar

    By William Wong, May 16, 2012

    MIPS Technologies has a new name for its product family, Aptiv. The family is divided into three performance solutions including proAptiv, interAptiv and microAptiv.

  • Soldering And Beer—What A Mix!

    Soldering And Beer—What A Mix!

    By William Wong, May 09, 2012

    Hand soldering may not be an option for production hardware but it is still actively used by hobbyists and prototypers so SparkFun wanted to see who was the fastest on the solder gun.

  • Three Core Micro Pushes Powertrain Performance

    Three Core Micro Pushes Powertrain Performance

    By William Wong, May 09, 2012

    Freescale's latest Qorivva, the multicore MPC5746M, is built around three e200z4 cores. Two can operate in lockstep.

  • Design Custom Chips That Maximize Battery Life

    Design Custom Chips That Maximize Battery Life

    By Navraj Nandra, May 09, 2012

    Synopsys' Navraj Nandra uses a hypothetical tablet computer to explain ways to save power in a new design through better custom-chip design: in the USB driver (and USB alternatives), colapsible power supplies,and new sleep states.

  • FPGA Design Suite Generates Global Minimum Layout

    FPGA Design Suite Generates Global Minimum Layout

    By William Wong, April 26, 2012

    Users of Xilinx’s Series 7 FPGAs will have a choice between two development tools. The Vivado Design Suite supports all of the Series 7 FPGAs and will be the development tool for all future FPGAs from Xilinx

  • 22nm 3D Transistor FPGA Packs In Hard Core IP

    22nm 3D Transistor FPGA Packs In Hard Core IP

    By William Wong, April 26, 2012

    Achronix Semiconductor's latest Speedster FPGA is packed full of hard core interfaces such as PCI Express. It is based on Intel's 22nm FinFET transistors and targets high performance applications.

  • What's The Difference Between ONFI 2 And ONFI 3

    What's The Difference Between ONFI 2 And ONFI 3

    By Bob Pierce, April 24, 2012

    At 400 M transactions/s, ONFI 3 runs at twice the performance of the previous ONFI 2 specification. ONFI 3 also offers useful features such as on-die termination, reduced signaling voltage, warm-up cycles, and volume addressing.

  • Kit Generates Virtual Platforms With Power Debugging Support

    Kit Generates Virtual Platforms With Power Debugging Support

    By Bill Wong, April 14, 2012

    Syynopsis' Virtualizer Development Kit (VDK) generates Arm architecture virtual prototypes suchas quad core Cortex-A15s or big.LITTLE platforms. It generates targets for software developers.

  • Multitouch Sensor Brings Flexibility To Design

    Multitouch Sensor Brings Flexibility To Design

    By Bill Wong, April 13, 2012

    Atmel is know for its maXTouch chips but now it is moving into the the sensor side with its flexible XSense technology.

  • Generator Delivers Multiport Embedded Memory Designs

    Generator Delivers Multiport Embedded Memory Designs

    By Bill Wong, April 12, 2012

    Memoir's Renaissance tool generates multiport memory designs based on single port memory. It can provide a unified memory system for custom SoC designs.

  • Take The LRDIMM Challenge To Boost Server Speed, Capacity

    Take The LRDIMM Challenge To Boost Server Speed, Capacity

    By Doug Daniels, April 11, 2012

    LRDIMM offers a streamlined upgrade path that brings two to three times higher capacity—using less power—than existing RDIMM technology.

  • Tiny Transistors! Giant Molecules! Moore’s Law Crashes Into The Laws of Physics

    Tiny Transistors! Giant Molecules! Moore’s Law Crashes Into The Laws of Physics

    By Jerry Twomey, April 09, 2012

    The evolution of the transistor has seen expensive failures, billion-dollar success stories, and a fair share of missed opportunities. Digging back in the literature when single transistors were coming to market, the perspective is interesting.

  • Heterogeneous 3D IC Test Vehicle Uses CoWoS Process

    Heterogeneous 3D IC Test Vehicle Uses CoWoS Process

    By Paul Whytock, April 03, 2012

    Altera Corp. and the Taiwan Semiconductor Manufacturing Company (TSMC) have jointly developed the world’s first heterogeneous 3D IC test vehicle using TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process.

  • Move Over, Moore’s Law—Here Comes 14 nm

    Move Over, Moore’s Law—Here Comes 14 nm

    By Paul Whytock, April 03, 2012

    Moore’s Law has been an influential parameter in driving IC performance forward. For decades, the number of transistors per circuit has doubled about every two years. But is this pace about to be overtaken? Developers of the 14-nm process and FinFET technology think so.

  • Make The Most Of Your MCU Sleep Modes

    Make The Most Of Your MCU Sleep Modes

    By Anders Guldahl, March 29, 2012

    Most modern MCUs have more than one low-power mode, ranging from a light sleep or standby mode through deep-sleep to off. However, the power savings available from lower-energy sleep modes come at a price. Energy Micro's Anders Guldahl explains how to optimise a design by finding the lowest power sleep mode that provides an adequate response time.