New processors from the likes of AMD, Intel, and Nvidia extended performance in 2012. Yet several other emerging devices pushed the technology into new areas: Everspin’s spin torque MRAM, now in DDR3 dual-inline memory modules (DIMMs); Microchip’s capacitive gesture controller; IDT’s NVMe controller; and Arm’s 64-bit Cortex-A50.

MRAM DRAM Targets The Enterprise

Everspin is using MRAM technology to move us backward in time (see “Moving Back To Magnetic Storage”). Well, not quite. By breaking the 64-Mbit barrier, its latest spin torque MRAM technology now can be used in main memory applications, not just niche applications (see “Magnetic DRAM Arrives”).

The company also has delivered a DDR3 MRAM DIMM based on the new chips that’s compatible with the industry-standard 3.2-Gbyte/s bandwidth (Fig. 1). This nonvolatile memory module can compete with hybrid flash/DRAM solutions like Viking Technology’s ArxCis-NV, which also requires an external supercapacitor (see “Nonvolatile DIMMs And NVMe Spice Up The Flash Memory Summit”).

1. Everspin’s DDR3 DIMM holds 64-Mbit MRAM chips, not DRAM, providing nonvolatile main memory for host processors.

The DIMM can deliver more than 400k 4-kbyte write IOPS since there is no intervening PCI Express interface between the host and the storage. Likewise, an in-memory database is more efficient. This solution is more expensive than DRAM, requires more power than flash memory, and has a more limited capacity than DRAM. But it still it offers better overall performance per watt than the alternatives, and things will only get better as production ramps up and the technology continues to improve.

Capacitive Hand Waving

Like many of its competitors, Microchip has a wide range of microcontroller-based capacitive touch solutions (see “CAN MCUs Integrate 12-Bit ADC, mTouch Capacitive Touch-Sensing IF”). This year, the company turned its capacitive technology up a notch—actually, more like 15 cm in the air with its capacitive gesture controller (Fig. 2).

2. Microchip takes capacitive sensing to new heights for non-contact gesture sensing.

A 32-bit microcontroller handles the interface and basic gesture recognition, such as a flick, wave, and swirl. It has about a 200-Hz cycle time, so fine gestures like pinch and zoom will be added in the future. Compared to other 3D recognition systems, it also consumes very little power. For example, its wakeup mode uses only 150 µW.

Sensor implementation is simple and inexpensive. The system uses frequency hopping to reduce the effects of noise. Its sensing system can be combined with devices such as tablets and laptops to recognize hand gestures above the display. Or, it can be used in areas without a dynamic display associated with the interface such as a control panel.

NVM Express Gets Easier To Implement

NVM Express is one standard for linking flash memory to a host (see “What’s The Difference Between SATA And NVMe?”). It uses a standard interface via PCI Express to provide a scalable, high-speed link to high-performance microprocessors.

IDT’s NVMe controller sits between the PCI Express link and the flash memory controllers, so it can be used in a range of storage configurations (Fig. 3). Two versions are available (see “Controllers Speed NVM Express Delivery”). One handles 32 flash memory channels and uses a x8 PCI Express Gen 3 interface. The other handles 16 channels and uses a x4 PCI Express interface.

3. IDT’s NVM Express controller links flash memory to a host via PCI Express. It will be found on disk drive (a) and PCI Express card (b) form factors.

The controllers will be found on PCI Express cards as well as drives using the new PCI Express interface standard. Creating systems is simply a matter of form factor and selecting flash memory chips. The chip handles the NVMe protocol and interface. These memory subsystems will be driving the cloud and enterprise applications.

64-bit Arm Arrives

The 64-bit Cortex-A50 series is based on Arm’s ARMv8-A architecture (see “Delivering 64-Bit Arm Platforms”). The first two entries include the low-power Cortex-A53 and the high-performance Cortex-A57 (Fig. 4). They’re designed to compete with the 64-bit x86 platforms, but they also will address a wide range of applications including servers. They can be combined using Arm’s big.LITTLE approach (see “Little Core Shares Big Core Architecture”).

4. Arm’s Cortex-A50 series moves the architecture into the 64-bit realm.

The Cortex-A50 currently supports up to 16 cores tied together using the CNN-504 Cache Coherent Network. The cores can be linked to the Mali T67x general-purpose graphics processing units (GPGPUs) that are also tied to the fabric (see “Mobile GPU Architecture Supports Emerging Compression Standard”). The architecture includes support for virtualization and multimedia acceleration in a power-efficient package.

One big difference compared to the x86 solutions is the number of vendors supporting Arm’s Cortex-A50. System designers of everything from embedded systems to smart phones to servers and high-performance computing (HPC) platforms will have a wide range of options.

Given how interesting 2012 was in the digital realm, it will be fun to see where things go next year.