Mixed-Signal Simulator Speaks Verilog-AMS

Designers today find themselves adding more and more analog and mixed-signal content to their creations. And at nanometer geometries and gigabit speeds, digital circuits begin to look more analog than digital. It all adds up to enormous verification problems.

Synopsys' Discovery AMS, a mixed-signal simulator, allows designers to create entire designs with Accellera's Verilog-AMS language, launch all simulations from a single integrated control environment, and efficiently use parasitic data for post-layout analysis.

The tool is built upon the VCS simulator, the NanoSim fast-Spice simulator, and HSpice. All in all, it offers a built-in simulation control engine that provides intuitive design partitioning, a single engine to launch simulation runs, and a unified display of both analog and digital signals. This gives designers the flexibility, capacity, and accuracy required during the design and verification phases. HSpice, with foundry-certified device models, offers the simulation accuracy required for use with VCS during the design phase.

At the core of Discovery AMS is a direct kernel-to-kernel integration of the HSpice and NanoSim transistor-level simulators with the VCS digital simulator. This integration is optimized for performance, which ensures a minimal overhead due to the interfacing of the multi-domain simulators. The co-simulation is run as a single process without any overhead of inter-process communications, and it shares the same memory space.

Discovery AMS is also tightly integrated with Synopsys' Star-RCXT parasitic extraction tool to provide an efficient, hierarchical post-layout parasitic extraction and simulation flow. This interface ensures that NanoSim can read the hierarchical netlist and parasitic data from Star-RCXT, automatically handling any issues with hierarchy or name mismatches.

The interface between analog and digital simulation uses a domain-shifting mechanism for translation of logic-to-voltage and voltage-to-logic translations. This mechanism is automatically handled by the interface. A resistance-map table is used to equate the digital signal strength to a driving resistance for digital-to-analog translations, and MOSFET on-resistance to equivalent digital signal strength for analog-to-digital translations.

Discovery AMS comes with a GUI base simulation control environment that makes it easy to set up a mixed-signal multilevel simulation. The Discovery AMS GUI provides an intuitive environment for input file management and simulation setup and control. Once the design netlist is read in, the user can simply choose the level of abstraction for different blocks in the designs, such as Verilog, Spice, or Verilog-AMS, without making any changes to the original netlist files. The multilevel simulation can then be setup for an optimal tradeoff between accuracy and speed using the simple dialog-based interface built into the Discovery AMS GUI.

Simulation output from a multilevel simulation can be viewed in a single waveform window in Cosmos-Scope. Cosmos-Scope is a mixed-signal waveform analyzer with excellent measurement capabilities for waveform analysis.

Verilog-AMS, a language standard approved by the Accellera EDA standards body, describes the behavior of analog and mixed-signal designs. The language is made up of three key parts: Verilog-D for digital designs, Verilog-A for analog, and mixed-signal extensions to specify domain-shifting algorithms.

Discovery AMS supports the Verilog-AMS OVI 2.0 standard, with which designers can simulate behavioral models for their mixed-signal designs. This easy mechanism for specification of mixed-level systems lets designers explore different architectures independent of the underlying silicon technology. As the design cycle progresses and more complex abstractions for the various design components become available, the behavioral Verilog-AMS blocks can be replaced by more detailed models for higher-accuracy simulation.

A one-year license for Discovery AMS starts at $122,000. It's in limited, controlled availability now with general availability scheduled for March, 2004.