Testing software for new system-on-a-chip (SoC) designs prior to delivery of hardware is imperative for companies that want to get products out the door quickly. Unfortunately, even inexpensive SoC simulation hardware normally costs more than $150,000. These prices relegate this approach to hardware designers. But new hardware—Aptix's System Integration Station (SiS)—makes SoC design testing economical enough for regular use by software de-velopers. Its prices range between $50,000 and $100,000 (see the figure).
Cost-cutting measures start with Aptix's System Explorer. The hardware remains the same with SiS, but most of the development software is removed from the mix. This removal includes ap-plications that perform chores oriented around hardware design, such as system partitioning. Software developers rarely get involved in this aspect of system design, so the removal of these applications significantly simplifies the system.
In place of the hardware development tools, Aptix provides a simpler configuration download application. The application downloads a system design stored on a network and configures the FPGAs with the system design. Consequently, software developers can download their applications for testing and run them at real-time or near real-time speeds.
Most of the standard IP, such as processor and DSP cores and memory, are implemented as discrete devices. Software developers, then, can use ICE and other familiar debugging tools. SiS has external connections as well, making it usable with other components that may be part of a larger design.
About the size of a tower PC, SiS is relatively small and mobile. It easily fits into a developer's office or lab area.
For more information, point your browser to www.aptix.com.