To meet the high-speed broadband signal-processing requirements of emerging 3G wireless basestations, 3DSP has developed an advanced DSP core, the SP-20. Optimized for physical-layer signal processing, the UniPHY processor combines an accelerated version of 3DSP's super-scalar SIMD (super-SIMD) architecture and RISC-like DSP instruction set with a new expansion instruction mode.
To boost execution speed, these expanded instructions fully utilize all of the functional units, including memory and register-file bandwidth.
As a result, the processor can si-multaneously use all of its 10 functional units to provide nearly four times the processing performance of its predecessor, the SP-5. Plus, to ensure efficient code size and ease of programming for control code, it maintains code compatibility with older SP-3 and SP-5 DSP cores.
This device can perform eight 16-bit multiply-accumulate (MAC) and eight 16-bit add operations per cycle. That translates to 4-gigaMAC (GMAC) performance at a 500-MHz clock speed. The SP-20 has been architected to execute instructions for clock speeds between 400 MHz and 1 GHz.
The SP-20's core provides hardware optimizations for key communications algorithms like Viterbi, FFT, and FIR. Consequently, it can execute the Viterbi decoder for GSM communications in 608 cycles, versus 6314 cycles for the SP-5. Likewise, it can perform a 256-point complex FFT in 659 cycles, as opposed to 2263 for the earlier version.
The SP-20 core is partitioned into four units: the instruction fetch unit (IFU), the instruction decode unit (IDU), the address generation unit (AGU), and the execution unit (EXU). While the IFU interfaces with program memory to retrieve instructions for the core, the IDU handles the instruction decode and dispatch functions as well.
The AGU is responsible for generating the addresses for the data memory accesses. The EXU contains all of the arithmetic functional units, the register file, and the accumulators. Each functional unit provides temporary storage to minimize memory accesses (see the figure). The SP-20 has two pipe-lined datapaths, each having nine stages, thereby reducing the cycle count for critical communications algorithms.
According to 3DSP's founder and CTO, Kan Lu, the IC's de-sign is complete, and a development chip is expected to be realized in 0.13-µm CMOS by early next year. It's supported by its fully configurable DSP design platform, HiFI. 3DSP is also evaluating the option of implementing this core in FPGA technology. However, further de-tails weren't available.
For details, go to www.3dsp.com.