Although DSP functions can be implemented in field-programmable gate arrays, their full potential can't be realized due to the general nature of the FPGA architecture. To overcome that, the recently developed QuickDSP family of FPGAs provides a combination of embedded DSP building blocks and programmable logic flexibility. The new family includes dedicated multiplier-and-arithmetic blocks in addition to the programmable logic and memory blocks that are employed on previous members of the company's FPGA family.
The resulting chips can perform DSP operations up to four times faster than traditional programmable-logic solutions for floating-point arithmetic, finite-impulse-response (FIR) and infinite-impulse-response (IIR) filters, color space conversion, fast Fourier transforms, and other functions. Initially, there will be four members in the QuickDSP family. The largest member will contain 18 embedded computational units (ECUs), with each unit consisting of dedicated 16-bit adders and registers and an 8-bit multiplier.
Each ECU is connected to the programmable-logic array, as well as to the RAM-block array. This setup lets data flow between all three sections of the chip. A three-bit instruction set—sequenced from the logic array, memory, or external pins—dynamically configures each ECU for any of eight possible operations. These operations include flow-through multiply, add, multiply-add, and multiply-accumulate.
Also, each basic logic cell in the FPGA has been enhanced, compared to cells in the company's previous FPGA family. The cells have a higher fan-in capability, and they can provide up to six independent outputs thanks to an additional multiplexer and register in the cell. The extra register supports applications such as pipelining, so the cell doesn't get "wasted" just to implement the pipeline register. Furthermore, designers added four PLLs/DLLs to the chip to provide clock multiplication or division over a 25- to 250-MHz frequency range. Jitter can be kept to less than 200 ps, thanks to the PLLs/DLLs. Nine global clock and control networks are on the chip—one is dedicated to maintain a skew of less than 150 ps, and the other eight are programmable.
The input data to the ECUs can come from any source in the chip. This allows the data flow to be altered dynamically, enabling the chip to handle variable-coefficient DSP applications. Designers then can realize complex single- or multi-sampling algorithms that use single or multiple data paths. The chips in the family support single-clock-cycle, 8- to 32-bit arithmetic functions with no pipelining, including multiplication operations at frequencies up to 220 MHz and additions up to 394 MHz. On-chip memory ranges from 46 to 82 kbits of dual-port SRAM.
The four family members include the QL7100, 7120, 7160, and 7180. They contain 292, 373, 558, and 662 kgates and 10, 12, 16, and 18 ECUs, respectively. RAM capacities start at 46 kbits and increase to 55.3, 73.7, and 82.9 kbits, respectively. Maximum I/O pin counts range from 256 to 512 pins, but packaging options allow less than maximum I/O configurations to lower costs. Each I/O cell includes three registers. The I/O cells are set up in eight banks, each capable of 2.5- or 3.3-V signal levels. The I/O lines can implement LVTTL, LVCMOS, PCI, GTL+, SSTL 2 or 3, and other popular interfaces.
Software to support the DSP capability also is available from the company. In addition to the company's QuickWorks design tools, a DSP wizard package lets the user create optimized functions such as fixed and floating-point arithmetic logic, as well as FIR and IIR filters, with just a few mouse clicks.
Prices for the QuickDSP FPGAs start at $19.95 apiece for the QL7100 in 50,000-unit quantities. The first unit to be sampled will be the largest device, the QL7180. Expect samples in the second quarter. The remaining devices will be sampled in the third quarter.
QuickLogic Corp., 1277 Orleans Dr., Sunnyvale, CA 94089-1138; Chuck Tralka, (408) 990-4000; Internet: www.quicklogic.com.