Jazelle | Espresso | Lightfoot | |
Company | ARM | Aurora VLSI | Digital Communications Technologies |
Processor type | Internal extension to CPU | 32-bit Java CPU | 32-bit Java CPU |
Dispatch method | On memory address | Executes bytecodes | Executes bytecodes |
Registers | Uses host CPU registers | Stack (eight 32-bit registers) | Stack (eight 32-bit registers) |
Bytecode coverage | 60% (140 of 234) | 90%+ (14 with software assist) | 100% |
Distribution | As part of ARM processor IP | As IP core | As IP for FPGAs, ASICs |
Number of gates | 12,000 | (Not available) | 25,000 |
Clock rate | 80 to 200 MHz | 140 to 400 MHz | 40 MHz |
Miscellaneous | Extensions for ARM7, ARM9 | Two-way superscalar, five-stage pipeline | 8-bit program memory |
Jazelle delivers eight times the performance gains of Java software JVM. Jazelle does 6.0 Caffeine Marks per megahertz and takes roughly 12,000 gates. An ARM 926EJ delivers 1000 Caffeine Marks at 200 MHz. Jazelle is implemented as an additional path in the instruction-stream decode. It extends the five-stage ARM9 pipeline to six stages. www.arm.com.
See associated figure.
Aurora also fields a low-power core, DeCaf. Both cores are available in versions that also execute C and C++. DeCaf power consumption is around 2.0 mW/MHz (0.18 µm). DeCaf delivers 20,000/35,000 Caffeine Marks (200/400 MHz). It executes four instructions/cycle or seven bytecodes/cycle. http://vodka.auroravlsi.com.
See associated figure.
The ALU incorporates a 32-bit barrel shifter and a 2-bit step multiplier. (It takes 16 cycles for a 32-bit multiply.) The CPU implements an 8-bit "bytecode" instruction memory interface (24-bit address). Data memory is supported by a 24-bit address, 32-bit memory path. The Java core supports J2ME, JavaCard, and C. Also, the core is extensible; users can add additional instructions. The soft core is available as a VHDL IP for ASICs and for Xilinx FPGAs. On a Xilinx Vertex-II FPGA, the core requires 1710 CLBs. The core supports J2ME, JavaCard, KVM, and JINI. www.dctl.com.
See associated figure.
JVXtreme | JStar | XPRESSOcore | |
Company | InSilicon | Nazomi Communications | Zucotto Wireless |
Processor type | Java Coprocessor | Java Preprocessor | 32-bit Java Processor |
Dispatch method | Via coprocessor instr. | On memory address | Executes Java bytecodes |
Registers | Uses CPU registers | Uses host CPU registers | Stack |
Bytecode coverage | 87 most common byte codes | 70% (160 of 227) | All bytecodes except JVM, file, and interrupt management |
Distribution | IP (Verilog) | As IP | IP core |
Number of gates | 35k | 30k | 60,000 |
Clock rate | 200 MHz | 50 MHz | 150 MHz |
Miscellaneous | ARM9 coprocessor, RTL core | Coprocessor for ARM, MIPS, Lexra | 22.5 Caffeine Marks/MHz |
The XPRESSOcore 150 includes a 32-bit data bus and supports integer types up to 64 bits. It implements static and dynamic branch prediction. The ALU includes a 16-bit modified Booth multiplier. The processors support low-power, wireless operation. The Xpresso 100 delivers 9 Caffeine Marks/MHz, at 40 MHz. It has a Bluetooth baseband controller and optional Bluetooth upper stack, five 16-bit timers, two USARTs, and a codec port. www.zucotto.com.
See associated figure.