The concept of 1-Transistor Random-Access Memory (1TRAM) was first introduced by MoSys Inc. and manufactured by Taiwan Semiconductor Manufacturing Co. (TSMC) in a standard CMOS process. 1TRAM uses a planar DRAM cell that's similar to a conventional DRAM cell, except the cell capacitance is smaller (see the figure). Designers can then craft a smaller cell in a planar CMOS-compatible fashion. A smaller cell size also results in a smaller product die area and leads to higher yield during manufacturing.
The major challenge for such a novel cell is to keep the charge-sensing margin at an acceptable level during the read operation. DRAM designers deal with it by keeping the charge-sharing ratio CCELL/(CBL + CCELL) to roughly 20%, with CCELL being the cell capacitance, and CBL a corresponding bit-line capacitance. If CCELL is reduced, designers can keep the charge-sharing ratio down by reducing bit-line capacitance. The architecture makes bit lines shorter and partitions memory into a large number of small banks. This unique partitioning is characteristic to 1TRAM designs.
In contrast, conventional commodity DRAMs don't use many small banks. That's because the small cell size isn't compatible with the coarse peripheral-circuitry design rules. It's then difficult to lay out a multibank memory with high array efficiency. However, the 1TRAM memory has tight logic-technology design rules coupled with a cell size larger than that of commodity DRAM, allowing a more efficient multi-bank layout. Finally, the memory cell's simple structure enables better control of hard defects in a fab line.
Using many small banks offers performance advantages like fast speed and low power—due to physically shorter bit and word lines—and low CCELL. A wider variety of memory interfaces can be introduced with the multibanking architecture because it permits fast purely random access—as fast as SRAM (hence, MoSys' brand name of 1T-SRAM). This in turn gives designers greater flexibility by enabling them to choose from a wide variety of logic-to-memory interfaces.
1TRAM Applications: According to the International Technology Roadmap for Semiconductors, system demands for embedded memory out pace SRAM scaling abilities. Consequently, denser embedded-memory technology must be incorporated. 1TRAM memory should find its way into embedded high-density memory applications because it has the highest density among CMOS memory technologies.
A variety of applications uses 1TRAM. Digital signal processing is a wide-open arena, while consumer chips for complex graphics and audio require extensive data storage during processing. In the past, makers of digital-camera, camcorder, and DVD-ROM chips used off-chip low-cost DRAM or embedded SRAM. Today, the memory content balloons from 2 to as high as 16 Mbits per chip, and embedded SRAM becomes pricey in cost-sensitive consumer products. Therefore, integrating memory on-chip will save power, simplify product logistics and board design, and accelerate bandwidth.
Networking offers another application area for 1TRAM. Embedded memory is used as an address table for switches and routers, with demand for density skyrocketing from 4 to as much as 80 Mbits per chip. In fact, networking chip companies were the first to adopt 1TRAM in mass production for Gigabit Ethernet applications.
This simple 1TRAM cell structure is shown from the side (a) and the top (layout) (b).