For most of its history, the semiconductor industry has most visibly appeared to focus on digital technology due to its predictable scalability. That has resulted in a less active focus on analog development and education. In turn, this has created an industry that's somewhat deficient in analog expertise. Additionally, today's tool support and process technology advances favor digital design, primarily because most electronic functions can be performed using digital technology.
Ironically, though, as life becomes increasingly digitized, there's a rising need for technology capable of measuring, interpreting, and interfacing to continuous real-world properties like voice, sound, temperature, and communication signals. The expanding use of the Internet, and wired and wireless communications devices, requires both analog and digital functionality.
The effort to reduce the cost and size of the end-system devices has spawned the system-on-a-chip (SoC) era. This age requires not only analog and digital expertise, but also knowledge of how to integrate these functions together. Shrinking time-to-market windows have prompted SoC designers to rely on a handful of silicon intellectual property (SIP) suppliers to deliver reusable mixed-signal cores. But, oftentimes technology touted as reusable hasn't actually been designed for reusability.
The architectural decisions made during an IP block design have a lasting effect on integration time and core performance. In order to ensure reusability, SIP vendors must design-in features that enable straightforward migration and porting.
First and foremost, all SIP, but especially analog SIP, must be delivered in a mainstream digital CMOS process. Because the majority of ICs today are fabricated using digital CMOS, this ensures that the technology can be integrated into a variety of devices from multiple customers. Analog-specific processes often require special process steps, which could limit foundry selection, decrease yield, and increase manufacturing cost.
Performing system functions digitally provides an optimal combination of economy and performance. Digital blocks port and migrate more easily to advanced process technologies with lower power and smaller die sizes. On the other hand, analog blocks implemented with more "tuned" processes are sensitive to process parameter variations and must be resimulated and reverified with each new process.
Yet, in cases where only analog will do the job, analog SIP can be reused. For those situations, it must be designed with built-in tolerances for variations and advances in process technology. By designing analog blocks to a wider design margin and allowing for larger design rules, mixed-signal cores can be reused in multiple products today. These cores can then be migrated for use in next-generation designs.
Additionally, state-of-the-art process technologies as low as 0.13 µm, and possibly smaller, let designers keep internal analog circuitry at 3.3 V. Therefore, analog blocks will be able to migrate more easily with digital technology advancements. That's possible because designers can leverage dual-oxide approaches which allow dimensions as thin as 65 to 80 Å to fabricate high-performance devices and thicker oxides for devices that must tolerate higher voltages.
Still, there are other challenges associated with reusable analog design. Because the majority of today's CMOS wafer capacity is allocated for digital products, device models and other process characterization data needed for proper analog design aren't available. As a result, a full fabrication spin is typically required in order to optimize analog blocks. In designs requiring analog technology, options can be included that allow circuits to be optimized for the process through a metal-mask change, or by digital programming.
Architectural features that simplify testing for analog must also be offered. Once integrated, cores become difficult to access, making it hard to identify problem sources. Designers need to be able to quickly verify performance and pinpoint design flaws so that costly design iterations are avoided. The SIP architecture must be conducive to embedded testing in order to provide a high level of confidence in the design's robustness.
Multiple test approaches exist for verifying analog functionality. One method allows for block-by-block testing, which provides more detailed data than testing the entire core as a function. By providing access to the analog block's interface pins, designers can efficiently test the core's analog and digital portions using low-cost mixed-signal testers. These testers can be applied to high-frequency blocks too, through down sampling—dividing the output so that it comes out at a lower frequency—and confirming that the design performs to specifications.
Another method, analog built-in self test (BIST), eliminates the need for a mixed-signal tester. The analog is tested as an entire function using dedicated on-chip logic.
The pervasive understanding of digital design practices, though, is moving the industry to develop methods of testing analog using digital testers. Embedding on-chip DACs and ADCs allows digital testers to apply a digital stimulus to an analog block and convert its analog output back into a digital vector. Known as "analog loop-back," this enables digital test engineers to use digital test programs and testers to verify analog performance without extensive analog expertise.
It's possible to ease the integration of mixed-signal SIP. By designing architectures that can be easily adapted to changing environments, SIP vendors ensure reuse. Few companies possess the rare digital and analog expertise required to deliver a reusable mixed-signal design. But, those that do will surely succeed. These companies will become strategic allies for SoC designers who must deliver high-performance, cost-effective systems within shrinking time-to-market windows.