Affording more transistors on a single chip, Motorola Semiconductor's SMARTMOS7 smart-power process integrates microcontroller core, nonvolatile flash, and other memory types with analog and high-voltage power components on the same substrate. Designers at the company used a CMOS logic platform to achieve this integration.
With migration to deep-submicron CMOS, Motorola's latest smart-power technology boasts system-level integration with 65-V power MOSFETs. This development incorporates the capabilities needed for a broad range of voltage applications, from portable power management where the maximum voltage rating is 7 V, to high-voltage automotive needs where 50-V capacity is required.
Due to a thin epitaxial process and a limited thermal budget, the integration of high-voltage power structures and analog functions in a 0.35-µm CMOS logic platform was a challenge (see the figure). Designers overcame this hurdle through advanced implantation techniques in conjunction with clever engineering of doping profiles.
Unlike conventional diffused junction-based technology, the SMARTMOS7 implements high-energy implants prior to field oxidation to realize a thick field oxide in the drift region. Since no major thermal steps are involved after the field oxidation process, this flow also minimizes silicon damage caused by the advanced implantation process.
According to Bob Baird, technology manager for Motorola's SMARTMOS Technology Center in Mesa, Ariz., "The energies of the implant chain are carefully chosen to provide enough junction depth for breakdown voltage without adding any manufacturing complexity to the existing implantation process." Experimental work indicates that the new technique can achieve breakdown voltages as high as 88 V by further adjusting the doping profiles and controlling the junction between the p and n extensions.
"The process also offers a very low RDS(ON)," notes Amitava Bose, program manager at the technology center. "In fact, the process provides an optimum RDS(ON) × area, the figure of merit for an LDMOS transistor fabricated in a deep-submicron CMOS process."
As a result, the developers have been able to integrate 65 V, with a reduced-surface-field LDMOS power device with a wide safe-operating area, into a 0.35-µm CMOS logic platform. The figure of merit realized for the 65-V LDMOS is 0.56 mΩ × m2.
"This SMARTMOS7 technology has been specifically defined and driven in close collaboration with our power-management and audio IC designers worldwide," says Behrooz Abdi, general manager of Motorola's RF/IF division. "It allows us to integrate complex audio-processing functions with power devices on the same substrate to achieve the lowest system cost, size, and current drain in today's portable products."
The results of this development were presented at the recent International Symposium on Power Semiconductor Devices (ISPSD) in Toulouse, France.