Today's multimillion-gate FPGAs offer great promise for designers confounded by the limitations of traditional ASIC implementation. Increased time-to-market demands, the lower cost of FPGA development, and FPGA capacities well in excess of a million gates, are increasing the number of applications being realized in programmable form. From networking and telecommunications designers grappling with narrow market windows and evolving standards, to a broad scope of designers seeking low-risk rapid prototyping, the number of people turning to FPGA solutions is quickly expanding.
Taking full advantage of state-of-the-art FPGA technology, however, presents new and difficult challenges. As FPGA process technology migrates into the deep-submicron realm, interconnect-dominant delay begins to pose the same difficulties for FPGA designers that previously plagued their ASIC counterparts.
Traditional schematic or logic synthesis-based programmable design solutions, similar to the ASIC methodologies of three to fours years ago, lack the ability to adequately account for interconnect effects early in the design cycle. With today's highly complex circuits and relentless market pressure, it's more important than ever that accurate interconnect-related performance information become an integral part in early design processes.
Design automation is the key to enabling this new era of FPGA design. Unfortunately, simply extending interconnect-aware ASIC design technology to the FPGA domain won't work. The interconnect configurations and options unique to FPGA architectures can't be comprehended by utilizing ASIC physical modeling techniques.
Instead, new design-automation technology that's specifically targeted at FPGAs is needed. It must address the difficult task of bringing accurate information about the physical interconnection of a programmable circuit into the design process without extending design cycles. Luckily, FPGA design technology is evolving to accommodate designers in the deep-submicron era.
Particularly important is FPGA-based physical-synthesis technology. Physical synthesis factors a design's physical characteristics into the synthesis process. During this process, a design is optimized and implemented based upon not only traditional timing constraints, but also on physical constraints.
The nature of FPGA architecture makes it possible to perform physical-optimization techniques during the synthesis process. These might include such things as moving registers across regional boundaries to increase performance levels.
Physical synthesis offers significant productivity and performance advantages to FPGA designers. First, the use of physical constraints during synthesis results in greater accuracy in timing estimation. This eliminates time consuming and tedious design iterations that are common in traditional approaches.
Likewise, physical optimization during synthesis makes it possible to physically optimize a circuit for the best possible performance. Combined physical-synthesis and optimization techniques can have large cost benefits as well. In many cases, designers can implement a device in a lower-cost speed grade.
FPGA physical synthesis forms the critical link between state-of-the-art programmable technology and those designers seeking to leverage its unique advantages. Programmable technology certainly opens the door of opportunity for those faced with today's tough market realities.