Flexible Interconnect Acts As A "Bus Tuner" For Wireless-Bound SoCs

Dec. 16, 2004
Physical structures, advanced protocols, and extensive power-management capabilities all merge together on the SonicsMX. Developed by Sonics in conjunction with Texas Instruments, this suite of intellectual property and tools targets the design of...

Physical structures, advanced protocols, and extensive power-management capabilities all merge together on the SonicsMX. Developed by Sonics in conjunction with Texas Instruments, this suite of intellectual property and tools targets the design of low-power system-on-a-chip (SoC) solutions for wireless and handheld applications.

At the heart of SonicsMX lies a power-savvy flexible interconnect--200-mW idle power with seven high-performance ports and 13 low-performance ports. The interconnect supports crossbar, shared link, or hybrid technologies within a multithreaded and nonblocking architecture. TI initially used the suite in its OMAP2 media engine, but it's now available for general use.

SonicsMX combines moderate clock rates (100 to 200 MHz), mixed latency requirements, user-definable power domains, quality-of-service (QoS) management, security protection, and error management. The interconnect can support up to 20 initiators and up to 15 targets. Side-band signaling support (interrupts and DMA) is included.

Because of its flexibility, SoC designers can fine-tune the SMART (Sonics methodology and architecture for rapid time to market) interconnect specifically for their application, as well as manage all communications and multimedia convergence data-flow challenges. SonicsMX also supports the OCP-IP 2.0 socket protocol through an active decoupled approach. This lets SoC designers craft their cores and interconnect strategies in parallel. On top of that, it helps reduce the engineering overheads for future projects.

SonicsMX IP incorporates the system interconnect that provides low-latency memory references, peer-to-peer flows between processors, and the ability to cascade blocks for system expansion. Also part of the suite is the Sonics 3220 peripheral interconnect, which helps offload system interconnect from slow bandwidth I/O traffic. The suite's MemMax DRAM scheduler helps increase throughput with guaranteed QoS for memory-intensive data flows.

With the SonicsStudio tool suite, designers can configure the SonicsMX for specific implementations. It also helps analyze data flows and execute performance verification testing. An available SystemC model for SonicsMX further facilitates system modeling and verification using standard EDA tools.

Contact the company for SonicsMX licensing costs.

Sonics Inc.www.sonics.com

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