SRAMs Eliminate Idle Bus Turnaround Cycles

Bandwidth for high-speed networking applications has been broadened with the release of four configurations of a 4-Mbyte synchronous SRAM that is said to eliminate idle bus turnaround cycles. The memories' Zero Bus Latency feature guarantees speed-driven communications and networking customers 100% use of system bus cycles. Clock speeds of the pipelined SRAMs range from 100 MHz to 143 MHz, with access times starting from 5.0 ns to 4.0 ns. Depending on the application, performance of memory subsystems that support today's high-speed microprocessors reportedly can be improved by as much as 50%. The ZBL SRAM is housed in 100-pin TQFPs.