New York City’s borough of Manhattan is one of the most densely populated areas in the world, with more than 1.5 million residents in just under 23 square miles. But on weekdays, commuters and visitors more than double that number to above 3.6 million people, for an amazing density of over 157,000 people per square mile, or about 177 square feet per person.
That means if every person were standing equidistant in an equivalent open area, they would cover the entire space at just 13 feet apart! And that’s not leaving any space for streets, cabs, restaurants, or bathrooms. The answer, of course, is that during a typical weekday in Manhattan, most of the people are either above ground in office or apartment buildings or below ground in the mass transit system. To maximize the utility of limited space, we need to think three-dimensionally.
Into The Third Dimension
2012 was another banner year for low-power design, and the most significant change in the industry was the move to 3D transistors, or FinFETs. They provide not only a significant speed boost, but also the capability to cut dynamic power by half and static power by as much as 90%. Intel’s Ivy Bridge 22-nm processors debuted in late 2011 featuring 3D transistor technology (“Tri-gate” is Intel’s name for its FinFET technology), with all main product families available by mid-2012. Following close behind, theHaswell family will be further optimized at 22 nm for power efficiency, taking full advantage of the improving Tri-gate process technology.
TSMC is taking a slightly different route to 3D, instead focusing on its 3D IC die-stacking capabilities to improve on cost, space, and power and aiming for 3D transistors (FinFET) technology in the sub-20-nm nodes, starting with 16-nm test chips due this year. TSMC rival UMC has also announced plans for 20-nm FinFET introduction late this year. On the Common Platform front, IBM, Samsung, and Global Foundries also announced FinFET support, with roadmap support through 14 nm, and eventually down to 10 nm.
While many of the product announcements are “forward-looking,” it’s safe to say that the industry is making a strong move in the 3D direction, in particular for the benefit of power efficiency. This is the next big thing in low-power computing, and it will impact all facets of semiconductor design and manufacturing for many years.
Despite the promise of higher performance and better power efficiency, the move to FinFETs comes with quite a few new challenges. For example, the entire tool chain is impacted, including transistor-level process modeling and simulation, mask synthesis, physical extraction, and physical verification, in turn requiring careful re-characterization and validation of models and libraries for higher levels of abstraction and design. One of the goals for the introduction of this fundamental change in process technology is to maintain as much compatibility with previous design flows as possible to enable quick and transparent adoption.
For IP designers, the fin’s discrete sizing restricts the ability to tweak transistor widths for small changes in performance, one of today’s most common tools for optimization. Channel length variation and body biasing are also limited in value due to the intrinsic characteristics of the FinFET technology.
So while much of the technology hoopla occurred in 2012, 3D transistors are just getting started as the new vehicle to propel Moore’s law forward for the next decade. The next few years should be very interesting as the benefits of this technology are seen in products from smart phones to servers.
But as with most real-world phenomena, 2012 is just the year that 3D grabbed most of the attention. Originally proposed in 1999 by a group from the University of California, Berkeley, FinFETs have been 13 years in the making, with huge R&D investments in manufacturing technology and software support to get us to this phase.
In the epic space battle at the Mutara Nebula between Captain James T. Kirk and Kahn Noonien Singh in “The Wrath of Khan,” Spock observes of Khan at the critical turning point of the battle, “He is intelligent, but not experienced. His pattern indicates two-dimensional thinking.” Luckily, we are intelligent, experienced, and thinking three-dimensionally!
Cary Chin is director of technical marketing at Synopsys Inc., responsible for the Discovery Low Power Verification solution. His background at Synopsys is in R&D where he has managed the Power Compiler, Primepower, PrimeTime PX, and Design Compiler FPGA products. Prior to joining Synopsys, he held senior management positions at Sun Microsystems, SynTest Technologies, and Viewlogic Systems. He holds undergraduate and graduate degrees in electrical engineering from Stanford University. He also has taught computer science and programming classes from second grade computer lab up to the collegiate level at Stanford. In his spare time he teaches violin and viola, serves as president of the Palo Alto Chamber Orchestra, and enjoys playing and coaching chamber music.