Once IC fabrication is complete, engineers use fault models to create test patterns that detect defects. These fault models are typically abstractions of defect behavior based on our experience and observations of how a defect affects the circuit operation. The fault models, which represent defects with simple properties, are easy for automatic test-pattern-generation (ATPG) tools to use, and patterns are usually created from design-gate logic behavior. This means that we apply these tests at the gate level (i.e., to standard cell inputs), but we might not reliably detect defects that occur within the cells.
To catch cell-internal defects, you can perform a characterization of defects based on the library cell’s physical design to produce a set of cell-aware faults that are also easy to use with ATPG tools. Thus, we use both the actual cell-internal physical characteristics and expected defects to define and target faults. Overall, cell-aware fault models significantly improve defect detection. This article describes the main differences between traditional fault models and cell-aware models from defect simulations.1
Table of Contents
- Traditional Logic-Based Fault Models
- The Pursuit Of Better Test Quality
- Difficulty Applying Supplemental Pattern Types
- Cell-Aware Fault Models
- Silicon Results
The typical baseline for IC production test consists of pattern sets based on the stuck-at and transition fault models, which detect most defects. We base both models on the concept of structural test. Instead of testing the overall design entity, testing is performed on the lowest-level design components and their connections.
Library models or cells are the lowest-level design component, instantiated in the design as gates. They can be simple primitive logic elements (e.g., buffers, AND gates, and other basic logic functions) and larger components comprising multiple primitive functions. Libraries for any given fabrication technology include different library views for time-based simulation tools, physical placement tools, ATPG, and more. The ATPG library view maintains models that only describe the logical operation of the library cells.
Stuck-at and transition fault models describe very basic defect effects. Stuck-at faults model both stuck at a logic-0 state (stuck-at-0) and stuck at a logic-1 state (stuck-at-1). Every gate pin in the design may have a stuck-at-1 and stuck-at-0. ATPG tools target these faults and perform fault simulations to ensure that the basic stuck-at fault behavior is detectable.
Fault targeting and simulation starts by exciting the fault. Here, upstream logic is sensitized so the fault-free state is expected, and then the fault is propagated to an observe point. Stuck-at faults are based only on the logic operation of the gate at which the fault is located and propagated through. For example, a stuck-at-0 fault at the D0 input of a 3:1 multiplexer only needs to excite a logic 1 at the D0 input (Fig. 1). The D1 and D2 inputs make no difference in propagating the D0 value in the 3:1 multiplexer logic model. Thus, the values at D1 and D2 are irrelevant.
A similar situation exists for a transition fault model, defined as a slow-to-rise and slow-to-fall fault at every gate pin. When targeting or simulating a transition fault at a gate pin, only the gate’s logic behavior is considered.
Overall test quality continues to improve thanks to the introduction of newer fault models over the years. They have different targets and ATPG algorithms, but they still only define targets at the cell I/O or the interconnects between cells.
More recently, greater attention has focused on the problem of detecting defects not covered by traditional standard fault models, and developing techniques to target them. We have successfully applied newer test strategies—such as N-detect, embedded multi-detect (EMD), gate-exhaustive (GE), and others—to deal with those uncovered defects.
The N-detect fault model and patterns, also called multiple detect patterns, represent a variation of stuck-at and transition fault models. The main difference is that for N-detect patterns, users can define a minimum threshold for the number of detections desired for each fault. ATPG utilizes a logical netlist and propagates faults through gates based on the gate logic behavior. N-detect patterns aim to detect interconnect bridges without requiring knowledge of the circuit topology.2 As a result, the test target is interconnect bridges, but there’s no simulation or information about the location of these bridges.
N-detect patterns improve the statistical probability of detecting bridges. Each new detection of a fault will present randomly varied values on surrounding logic and random ATPG targeting for fault excitation and propagation. This improves chances of detection by targeting the same fault multiple times under different conditions. However, this also typically increases the pattern set by a factor N and, in turn, substantially increases test cost.
An enhancement to N-detect patterns, called “embedded multiple detect” (EMD), performs multiple detect analysis during the normal ATPG process using unspecified scan cells.3 Consequently, the N-detect profile is better than that of stuck-at or transition patterns, but without increasing pattern size.
Another fault model that intends to detect bridge defects is the “deterministic bridge” model.
With this fault model, extraction tools use the design’s physical layout to identify the nets most likely to have a bridge between them. We define each deterministic-bridge fault location as a net pair. ATPG will propagate the fault through gates based on logic behavior, much like standard stuck-at and transition ATPG.
In practicality, the vast majority of deterministic bridge faults are detected by standard stuck-at and transition fault. However, top-up patterns for the missing bridges uniquely detects defects in production.
The transition fault model is effective in detecting most timing-related defects. However, it only detects gross delay defects. The path of the slow 0-1 or 1-0 defect isn’t important for transition ATPG. Timing-aware ATPG targets “small delay” faults. It uses the design timing information when targeting faults to ensure that the fault propagates along the path with minimum slack. The only difference in the ATPG between transition patterns and timing-aware is path selection for exciting and propagating the fault. Like transition patterns, it uses logic behavior of gates for propagation.
Several fault models can detect defects, but they don’t target a particular defect behavior. We often refer to these as fault models for unmodeled defects.
Logic built-in self-test (BIST) frequently comes into play during production to increase the detection of manufacturing defects. The actual types of defects that it uniquely detects aren’t always clear, because the stuck-at and transition coverage of the logic BIST patterns often mirror traditional stuck-at and transition ATPG coverage. One explanation of unique detection is thought to derive from the very high multiple detect rates provided by logic BIST.
“Gate-exhaustive” (GE) testing applies every combination of each device gate’s inputs. It doesn’t target a particular type of defect, but in theory it should improve detection of defects inside the gates/cells and between interconnects. Thus, GE ATPG doesn’t use logic behavior to propagate a fault model from the input to output. Unfortunately, because so many possible combinations exist at every gate input, the amount of test patterns for a production design would be unreasonable to apply in production.
The aforementioned fault models all provide some amount of unique defect detection, but their enormous pattern sizes inflict cost damages. Embedded compression helps, but too many patterns still exist to apply all of them. More important is that many pattern sets for these fault models have limited weighted value of unique defect detection versus pattern size. For example, a GE pattern for a four-input AND gate would have 16 possible input combinations. However, it’s unlikely that all 16 patterns would turn up unique defects.
All of these fault models are designed to cover the inter-cell connections and cell logic behavior. They may cover intra-cell interconnect lines, but only by chance. Because we’re seeing an increase in cell-internal defects on total test coverage, a new methodology to directly target library cell-internal defects has become essential.
A methodology known as cell-aware (CA) ATPG approaches the fault modeling and ATPG process from a different angle. Instead of basing fault models on a general behavior to describe a defect, CA focuses on modeling the circuit’s behavior in response to defects inside the gates or cells.
Some unmodeled defect ATPG, such as GE ATPG, also can detect defects within the cells, but they’re inefficient. The unique value of cell-aware ATPG is a characterization process to model and convert defect behavior within a cell into a fault model that can be applied by state-of-the-art ATPG tools. One major difference separates CA ATPG from traditional fault models: The cell-aware fault model is carefully produced by locating and simulating defect behavior.
CA ATPG combines layout extraction with an analog fault simulation and synthesis to create fault models for the library cells. After completing the characterization process, these CA fault models are used to generate high-quality test patterns. This significantly reduces the defect level of delivered ICs. The complete flow is a mixture of state-of-the-art tools and new algorithms developed for the methodology (Fig. 2).
Unlike ATPG based on other fault models, CA defect characterization finds the unique input combinations as simulated against expected defects. Therefore, each fault model produced by the CA characterization process is efficient and known to provide value. This is different from stuck-at and transition faults, which are based only on faults outside the cell. CA ATPG also differs from GE and logic BIST, which must apply a huge amount of patterns. That’s because one never knows the patterns that will uniquely detect defects. CA ATPG is potentially much more efficient than ATPG for unmodeled defects.
We can show how CA ATPG is better for the layout of this three-input multiplexer (Fig. 3). A pattern with D0=0, S0=0, and D1=1 is necessary to detect the cell-internal bridge that can occur between S0 and D1 in the cell layout. Note that a different layout of a three-input multiplexer might not place the S0 and D1 metal where a bridge can occur between them. Traditional pattern types don’t care about the D1 input value, because it doesn’t change the logic behavior needed to propagate the D0 input. Moreover, it relies on chance that D1 would randomly be driven to a logic 1 for this pattern.
To demonstrate the benefit of the cell-aware methodology, we evaluated 10 different 65-nm industrial designs (see the table).4 The average defect coverage is 1.2% higher than that of coverage simulations for basic SA and EMD patterns, which is highly significant for high-volume designs or designs that must approach “zero defects.” The total amount of additional CA patterns falls in the range of 50% above the number of SA patterns for the 10 evaluated industrial designs.
Recently cell-aware test patterns were applied on 800,000 production devices from a 32-nm technology.5 This efficient cell-aware pattern set achieved a total defect rate reduction of 885 parts-per-million (PPM).
Cell-aware patterns clearly play an important role in improving production test. Often, the question is what the best mix of test patterns is. That’s because stuck-at, transition, and other patterns can all be effective in detecting defects.
The best approach is probably a combination of fault models. Cell-aware patterns catch defects inside cells based on their layout. However, other pattern types may be more effective in detecting defects between interconnects. A suggested approach is to characterize the effectiveness of various test types in production and adapt the pattern-type allocation accordingly.6
The key difference between traditional fault models and cell-aware ATPG is that cell-aware utilizes a characterization process to produce a fault model with values known to detect defects based on the cell’s physical layout. Traditional fault models use abstractions of defect behavior and don’t directly tie pattern sequences to expected defects that can occur within cells. As a result, CA ATPG patterns provide significant defect detection without dramatically increasing pattern count.
Cell-aware methodology is growing in popularity, especially for low DPM products. In addition to analyzing small-delay defects caused by cell-internal bridges, small-delay defects caused by cell-internal opens are being applied to production circuits.
- R. Press, “Understanding Cell-Aware ATPG and User-Defined Fault Models,” Electronic Design, Feb. 2012.
- B. Benware, et al., “Impact of multiple-detect test patterns on product quality,” Proceedings of IEEE International Test Conference, ITC, 2003.
- J. Geuzebroek, et al., “Embedded Multi-Detect ATPG and Its Effect on the Detection of Unmodeled Defects,” in Proceedings of IEEE International Test Conference, ITC, 2007, paper 30.3.
- F. Hapke, et al., “Defect-Oriented Cell-Internal Testing,” Proceedings of IEEE International Test Conference, ITC, 2010, paper 10.1.
- F. Hapke, et al., “Cell-aware library characterization for advanced technology nodes and production test results from a 32nm processor,” DATE 2012.
- R. Press, “Determining the best test patterns for production test,” Test & Measurement World, March 2012.