Cadence And Credence Partner On DFT Technology

June 24, 2002
With system-on-a-chip (SoC) complexity rising dramatically, so too has the total cost of testing these devices. A technology partnership between Cadence Design Systems of San Jose, Calif., and Credence Systems of Fremont, Calif., will create...

With system-on-a-chip (SoC) complexity rising dramatically, so too has the total cost of testing these devices. A technology partnership between Cadence Design Systems of San Jose, Calif., and Credence Systems of Fremont, Calif., will create design-to-production test methodologies based on an open architecture. As a result, users will be able to manage their test-methods portfolio across the supply chain, accelerating time-to-market and reducing overall cost of testing.

The companies plan major improvements in the design-to-production test flow by integrating test requirements into the design process. They'll also work toward open, industry-standard means of migrating those test parameters into the engineering validation and production test environments.

Initially, Cadence and Credence will integrate software to create a test-validation environment for the IC design-for-test (DFT) engineer. This software will be available through Cadence sales channels.

Verification design tools from Cadence (NC-Sim) will be combined with test automation and debug tools (Digital Virtual Test/Test Development Series) from Credence's subsidiary, Integrated Measurement Systems Inc., to build a streamlined design-to-production test flow.

The flow will encompass design implementation, test validation/debug, cyclization, and test program development. Both companies will devote engineering resources to the joint effort.

For details, go to www.cadence.com or www.credence.com.

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