From a silicon design perspective, the industry has long held the notion that power consumption can be reduced simply by porting chips forward to the next process technology node. Yet as more consumer electronics move from 130-to 90-nm mixed-signal ICs, power reductions no longer scale with technology advances and finer geometry. To select the most power-efficient chips, systems developers must look beyond process shrink capabilities and rely upon their semiconductor provider's intellectual property (IP) portfolio and design innovations.
The mandate to conserve power in consumer electronics speaks to the growth in portable products as well as to the need to improve reliability and minimize failure rates. Using hard-disk drives as an example, the demand for increased storage capacities in notebook PCs and handheld consumer applications is at odds with the power savings required to extend battery life and improve reliability.
Every doubling of capacity results in approximately a 40% increase in data rates (channel clocks) and servo rates (processor speed). Additionally, capacity is growing through improved error-correction circuitry. More powerful (and larger) circuitry is needed to fuel the capacity growth. The higher power—and corresponding temperature increases—at these faster data rates reduce drive reliability considerably, leading to potential failures in the drive's heads, media, and electronics.
Since disk drive silicon consumes half of a drive's power budget, the drive silicon is critical. The mixed-signal read channel is a prime candidate for improvement, given that its role in encoding and decoding data off a drive's magnetic platter makes it a dominant power user.
New 90-nm read channel IP consumes as little as one-third the power of equivalent 130-nm circuits, but only a small percentage of the total power savings results from the technology transition. The key reason is that analog circuitry can't ride the power curve to 90 nm. The analog side includes VGA blocks, continuous time filters, and voltage-controlled oscillators—circuits that require biasing with voltage headroom and linear amplification. These functions do not benefit from process shrinks, as the voltage headroom requirements are driven by the signals being used, not by the process.
Process shrink primarily reduces the dynamic power consumed in the channel's digital back end. A read channel's digital functions include the detector, encoder/decoder, and timing recovery, with power proportional to switching frequency. The relationship is:
In moving to a smaller geometry, capacitance (C) drops proportionally, and digital core voltage (V2) is lowered (typically to 1.0 V for 90 nm). This reduces the digital power consumption. But since the analog circuitry in an ASIC doesn't scale, the resulting mixed-signal reduction is smaller.
Another challenge, leakage current, increases through process shrink. Leakage power is important in battery-operated devices, as standby modes require extremely low power consumption. As silicon moves to finer geometries, sub-threshold leakage increases exponentially and other adverse elements are introduced, such as drain-induced barrier-lowering effects. Multilevel threshold techniques can ensure the devices are more thoroughly "off."
So, the notion that all power savings in mixed-signal ASICs come from process shrink is a myth. The more significant power savings come from the vendor's IP and innovation. Re-architecture in the areas of analog and digital circuitry is required to deliver significant power savings.
Examples include a switchable core voltage to provide lowest-power or highest-performance operation; highly programmable operating and power-management modes; novel filter topologies for low power; custom-designed, data-intensive blocks to reduce power and area; and analog circuitry capable of low voltages.
