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Design Automation Conference (DAC)
A 45th DAC Post-Mortem
By David Maliniak
Electronic Design
Last week's 45th Design Automation Conference (DAC) in Anaheim was my twelfth consecutive DAC, and it was surely the most interesting and different I've experienced in journalistic terms. Yeah, that was me traipsing around the show floor with my colleague Damian Mendez in tow, toting a great big video camera. It was my first experience in documenting DAC in video, and I would term it a success...
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Go To DAC, For Your Career's Sake...
By Limor Fix
Associate Lab Director, Intel Research Pittsburgh
45th DAC Chair
In order to have a long and successful career in the electronic design industry—whether you are a designer, engineering manager, or executive–there are three essential activities that you should do. First, enhance your skills and knowledge. Secondly, network with your peers. And last, monitor market trends.
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Previous coverage from DAC...
May 20, 2008: 45th DAC Takes The SoC Methodology Plunge
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| Editorial Video from DAC |
 When he’s not busy hosting DAC’s hottest party, Sanjay Srivastava, Denali’s president and CEO, kicks back and talks about developments in Denali’s lines of verification IP, memory controllers, and memory IP. Visit http://www.denali.com
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 President and CEO Isadore Katz of CLK Design Automation discusses CLK DA’s Amber family of transistor-level statistical static-timing analysis tools. Visit http://www.clkda.com
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 Dr. Michael Siegel, OneSpin Solutions’ product marketing director, spills the beans on OneSpin's SystemVerilog Assertions (SVA) library, which gives users of the company's 360 Module Verifier the ability to capture timing diagrams as SVA assertions. Visit http://www.onespin-solutions.com
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 Rich Faris, director of marketing at Real Intent, covers the latest developments for Real Intent's EnVision family of RTL verification software. Visit http://www.realintent.com
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 Lauro Rizzatti, vice president of marketing and GM of EVE-USA, shares the news of EVE's ZeBu-Personal, an affordable way to get emulation capabilities onto every engineering workbench. Visit http://www.eve-usa.com
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 Vincent Perrier, CEO of CoFluent Design, details CoFluent Studio v3, touted as the world’s first Eclipse-based graphical ESL modeling and simulation framework. Visit http://www.cofluentdesign.com
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 Larry Williams, Ansoft's director of business development, discusses the addition of statistical eye-diagram analysis of serial links to Ansoft’s Nexxim simulator. Visit http://www.ansoft.com
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 Synopsys's Saleem Haider, senior director of marketing, covers Synopsys's new Zroute routing engine for IC Compiler, which delivers multi-threaded capabilities as well as a DFM-centric sensibility. Visit http://www.synopsys.com
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 Scott Sandler, VP of worldwide corporate marketing and president of SpringSoft USA, explains how integrating the former Novas Software under the SpringSoft umbrella is a little like inverting an iceberg. Visit http://www.springsoft.com
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 Listen in as Dave DeMaria, Apache’s senior VP for chip-package-system products, covers Apache's Sentinel-PI, a global chip-package-system co-design and co-analysis tool for power integrity. Visit http://www.apache-da.com
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 It wouldn't be DAC without a chat with Gary Smith, the EDA industry's preeminent analyst and market consultant, who gives his take on the dominant trends in technology. Visit http://www.garysmitheda.com
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 Ashutosh Mauskar, VP of product and business development for Magma's Custom Design Business Unit, hits the high points of Magma's Titan chip-finishing suite, which marks Magma's thrust into mixed-signal design automation. Visit http://www.magma-da.com
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 CEO Jim McCanny of Altos Design Automation discusses the benefits of Altos's cell-characterization tools for deep sub-micron process technologies. Visit http://www.altos-da.com
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 Todd Cutler, senior manager for marketing and services at Agilent EESof EDA, covers the highlights of Agilent's offerings for analog/RFIC design engineers. Visit http://www.agilent.com
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 Let Joe Sawicki, VP and GM of Mentor Graphics' Design to Silicon Division, fill you in on Mentor's sharpening focus on IC implementation, and most notably the Olympus-SoC place-and-route system. Visit http://www.mentor.com
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 Winlei Lian, a field application engineer at Agilent EEsof EDA, demonstrates the company's wireless design library for its Advanced Design System (ADS), which is EDA software for wireless, RF, and microwave-IC design. Visit http://eesof.tm.agilent.com
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 Extreme DA's director of marketing, Graham Bell, covers the launch of Goldtime MXO, a timing analysis tool aimed at multi-mode, multi-corner timing optimization and signoff. Visit http://www.extreme-da.com
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 Mitch Dale, Calypto's director of marketing, takes you through the latest in the company's tools for RTL power optimization and sequential logic-equivalence checking. Visit http://www.calypto.com
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 XYALIS's founder and CEO, Eric Beisser, delivers the latest on his company's products for dummy metal filling to address CMP issues and mask-data preparation. Visit http://www.xyalis.com
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 Watch as IPextreme's CEO, Warren Savage, runs through the benefits of IPextreme's online CoreStore, where FPGA designers can find a free-of-charge, FPGA-optimized soft version of Freescale's V1 ColdFire core for Altera's Cyclone III FPGA. Visit http://www.ip-extreme.com/corestore
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 Sequence Design's CEO Vic Kulkarni paints the picture on his company's new PowerArtist tool, which takes a uniquely graphical – and colorful – approach to RTL power reduction for clocks, memory, and datapath. Visit http://www.sequencedesign.com
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| Other news from DAC |
A 45th DAC Post-Mortem
Last week’s 45th Design Automation Conference (DAC) in Anaheim was my twelfth consecutive DAC, and it was surely the most interesting and different I’ve experienced in journalistic terms. Yeah, that was me traipsing around the show floor with my colleague Damian Mendez in tow, toting a great big video camera. It was my first experience in documenting DAC in video, and I would term it a success.
Collaboration Provides Sub 65-nm Variation-Aware IC Design Flows
This week at the Design Automation Conference (DAC), Extreme DA and semiconductor foundry UMC announced their collaboration on variation-aware IC design flows for 65-nm and finer process technologies. Extreme DA specializes in IC performance and yield-improvement software. The jointly-developed design flows reduce uncertainty and predict performance and yield by analyzing timing behavior in the presence of process variations.
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