|
| CDNLIVE! EMEA 2008 - Call for papers now open! |
| |
28-30 April 2008
Hilton Munich Park
Munich, Germany |
| CDNLive! Silicon Valley 2007 Most Valuable Paper |
| |
“Translation of an Existing VMM-Based SystemVerilog Testbench to URM”
Kelly Larson, Verification Manager, Analog Devices Inc.
This paper describes the process of converting an existing testbench based on VMM class libraries to one based on URM class libraries.
|
| CDNLive! Silicon Valley 2007 People’s Choice Papers |
| |
Digital Implementation
"The Art and Science of Pin Placement for Hierarchical Floorplanning"
Jack Benzel, ASIC Engineer, Avago Technologies
This paper first covers motivations for and the basic concepts of pin placement, as well as more advanced topics covering the breadth of the Cadence® Encounter® digital IC design platform’s capabilities and limitations.
|
| |
Custom Design
“CDB to OA – The Migration Report”
Gernot Heiling, Senior Design Support Engineer, austriamicrosystems
This presentation provides an overview of the migration procedure including data validation, translation to the OpenAccess standard, and final verification of the translated data. It also provides detailed information about the challenges and pitfalls faced during migration and the in-depth cooperation with Cadence to finally end up with a qualified HIT-Kit for the Cadence® Virtuoso® custom design platform version 6.1 and OpenAccess.
|
| |
"Simplifying Vertical Reuse with Specman Elite"
Mark Strickland, Technical Lead, Cisco Systems, Inc. |
| |
"Predicting Physical Design Results Using Advanced Synthesis Features"
Shahzad Chowdry, Member Technical Staff, Symmid Semiconductor Technology |
| |
“Using Spectre RF Noise-Aware PLL Methodology to Predict PLL Behavior Accurately”
Helene Thibieroz,Staff Application Engineer, Cadence Design Systems, Inc. |
| |
“Cadence Allegro Editor (v 15.7) - Allegro Top 30 - Did You Know”
Vincent Di Lello, Senior PCB Designer, Kaleidescape Canada |
| |
“Signal Integrity and PCB Layout Considerations for DDR2-800 Mb/s and DDR3 Memory Systems”
Chris Brennan, PCP Designer
Christan Tudor, Signal Integrity Engineer
Eric Schroeter, PCB/Mechanical Designer
Heike Wunschumann, PCB Layout Designer
Syed Bokhari, Lead SI & EMC Specialist
Fidus Systems, Inc. |
| |
“Using Thermal Analysis as a Tool to Aid Analog Floorplanning”
David Schwan, Senior CAD and Layout Manager, Sirenza Microdevices Inc. |
| CDNLive! EMEA 2007 Best Paper Features |
| |
Methods to Improve Verification Quality on the Module Level - by Markus Gross, Siemens AG |
| |
How to use SPB 15.7 to Simplify your DDR Constraints - by Mike Veal, IBM Storage |
| |
CDB to OA -- The Migration Report - by Gernot Heiling, austriamicrosystems |
|
|
| |
|
|
|
GUC to Leverage CPF-Based Low Power Solutions to Accelerate Development of Consumer Products |
|
New Aspect-Oriented Generation Engine and Advanced Transaction-Based Acceleration; Supports Open Verification Methodology for SystemVerilog C |
|
Performance and Productivity Features of Latest Virtuoso Platform Now Supported by UMC's 65nm FDKs |
|
CPF-based Integrated Flow Enables G2 Microsystems to Deliver Ultra Low-Power Wi-Fi SoC |
|
Multi-Year Partnership to Provide Holistic Design Solutions to Drive Innovation and Shorten Product Time to Market for NXP |
|
Anchor Bay Adopts Cadence Incisive Xtreme III System for Verification of HDTV and Digital Video Products |
|
NEC Electronics America Uses Cadence Encounter for High-performance, Low-power ARM11 Processor |
|
What You Design Should Be What You Get, Says EDA Leader Cadence |
|
Cadence Accelerates Time-to-Volume for Advanced ICs with Model-Based, Variation-Aware Design Technologies; Provides 'WYDIWYG' Capability |
|
The "New Kit from Cadence Cuts Risk and Time for Adopting Functional Verification Methodology |
|
Cadence Extends DAM Solution with Acquisition of Design-side Litho and
Variability Leader Clear Shape Technologies |
|
Cadence and Mentor Graphics Deliver Interoperability with Open
SystemVerilog Verification Methodology |
|
Siemens IT Solutions and Services Adopts Cadence's Assertion-Based VIP to Speed Developement |
|
Cadence Strengthens DFM Core Technology and Solutions Through Acquisition of Invarium |
|
Jazz Semiconductor Teams with Cadence on Support for Cadence Rf and AMS Design Kits |
|
Toumaz Technology Achieves First Silicon Success with Cadence Virtuoso Multi-Mode Simulation |
| |
Attendance up 35 Percent at Cadence CDNLive! User Conference Held in Munich, Germany |
| |
Cadence Accelerates 45-nm Design with TSMC Reference Flow 8.0 |
| |
Cadence Improves Logic Designer Productivity through Enhanced Design-with-Verification Flow |
| |
Cadence Speeds RF PCB Design Cycle with New Allegro PCB Technology |
| |
Cadence Introduces Industry's First Complete Custom IC Simulation and Verification Solution |
| |
Cadence Revolutionizes Productivity for Next-Generation PCB Design with New Allegro Platform |
| |
Cadence Speeds Adoption of Wireless and Consumer Low-Power Designs with Low-Power Methodology Kit |
