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DDR4 speeds require key AC timing parameters such a timing and voltage of data input valid window to be defined and measured in a new way. The traditional measurement of data setup and hold time are no longer adequate to ensure accurate data transfer between DRAMs and memory controllers. The DDR4 specification addresses this issue head on by accounting for real-world random and deterministic jitter at a Bit Error Rate (BER) that assures system stability while eliminating costly and time consuming design cycles. This session will explain the new AC parameters in depth and show you how to measure them, allowing accurate device characterization and system validation without costly timing surprises at system integration.