Intel’s 82786 Intel’s First Discrete Graphics Coprocessor
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Intel saw the rise in discrete graphics controllers such as NEC’s µPD7220 (and even licensed it), Hitachi’s HD63484, and the several clones of IBM’s EGA, and conclude Intel was leaving a socket unfilled by them. Intel’s intention always was, and still is, to provide every bit of silicon in a PC, and a graphics controller would be no exception.
In 1986 the company introduced the 82786 (Fig. 1) as an intelligent graphics coprocessor that would replace subsystems and boards that traditionally used discrete components and/or software for graphics functions. It was designed to be used with any microprocessor, including Intel’s l6-bit 80186 and 80286 and 32-bit 80386.
The Graphics Processor (GP) and the Display Processor (DP) were independent processors in the 82786 (Fig. 2). The Bus Interface Unit (BIU) with its DRAM/VRAM controller arbitrated bus requests between the Graphics Processor, Display Processor, and the External CPU or Bus Master.
Intel made the argument that the integrated design of the 82786 would increase programming efficiency and overall performance while decreasing development and production time and costs of many microprocessor-based graphics applications such as personal computers, engineering workstations, terminals, and laser printers.
Compatibility with Intel microprocessors, the many device independent standards, and IBM Personal Computer bitmap memory format, combined with support for international character sets, multi-tasking, and an 8- or 16-bit host would make programming the 82786 flexible and straightforward claimed the company. The extensive features of the 82786 said Intel, would accommodate many designs. The list below contains some of the main features of the 82786.
- Integrated drawing engine with a high-level computer graphics interface instruction set
- Supports multiple character sets (fonts) that can be used simultaneously for text display applications, rapid pattern fill and International characters
- Hardware support for fast manipulation and display of multiple windows on the screen
- DRAM/VRAM controller supporting up to 4 MB of graphics memory, shift registers, and DMA channel, supports sequential access DRAMs and dual port video DRAMs (VRAMs)
- Fast bit-block transfers (bitbit) between system and graphics memory
- Supports up to 200 MHz CRTs or other video interface
- Up to 256 simultaneous colors per frame
- Programmable video timing
- IBM Personal Computer bitmap formats
Support for high resolution displays using a 25 MHz pixel clock enabled the 82786 to display up to 256 colors simultaneously, that was a biggie at the time. Systems designed with multiple 82786s or a single 82786 with VRAMs could support virtually unlimited color and resolution said Intel.
Key to the 82786 was its memory structure, it could access either graphics memory directly supported by the integral DRAM/VRAM controller or external system memory that resided on the CPU bus. When the 82786 accessed system memory, it controlled the bus and operated in Master Mode. The chip could also operate as a Slave with the CPU accessing the 82786 graphics memory and the internal registers. From the software standpoint, the 82786 accessed graphics and external system memory in the same manner. However, performance increased when the 82786 accessed its own graphics memory because the 82786 DRAM/VRAM controller accessed it directly without encountering contention with the CPU. Conversely, the CPU could access its own system memory more quickly than graphics memory because it did not encounter contention from the Display Processor or Graphics Processor.
Another feature of the 82786 was the bitmap organization. It replaced the traditional bit plane memory model and used sequential ordering (linear memory) which took advantage of the fast-sequential access modes of DRAMs or dual port video DRAMs (VRAMs) to gain performance (Fig. 3). The first commercial VRAM was introduced in 1983 by Texas Instruments, three years before the 82786, and was adopted by various graphics add-in board (AIB) suppliers, which was part of what Intel was reacting to.
The 82786 supported a packed-pixel bitmap organization for color in which all color bits for each pixel were stored in the same byte in memory. In the traditional bit-plane model, each plane defined separate color information. For example, a 4-plane bitmap described a bitmap with four colors. Each byte of memory contained one bit of color information for each pixel in the 4-plane bitmap. In the 82786 packed-pixel model, each byte stored data for two pixels.
The chip drew all geometric objects and characters and moved images within and between bitmaps. The GP created and updated the bitmap, executed commands placed in memory by the host CPU, and updated the bitmap memory for the DP. The GP high-level commands provided high speed drawing of graphics objects and text. It performed all those functions independently of the DP.
The DP traversed the bitmaps generated by the GP or external CPU, organized the data, and displayed the bitmaps in the form of windows on the screen. The DP had a video shift register that could assemble several windows on the screen from different bitmaps in memory and zoom any of the windows in the horizontal and/or vertical directions.
When the DP detected a window edge, it automatically switched to the next bitmap to display the subsequent window. Microsoft’s Windows 1 (Fig. 4) had come out and in 1986 version 1.02 and 1.03 were released so windows management was now important.
Essentially, the DP operated as an address generator that accessed appropriate portions of memory-resident bitmaps. The data fetched from bitmaps was passed to the DP CRT control1er, which displayed the bitmap data on the screen. The DP CRT controller generated and synchronized the horizontal synchronization (HSync), vertical synchronization (VSync), and Blank signals. The DP performed all those functions, independently of the GP.
The DP could operate as a Master. or a Slave based on the horizontal synchronization (HSync) and vertical synchronization (VSync) signals, which were set with the S(ync) bit in the CRT mode display control register. When the S bit was set to one, the DP was a slave with the HSync and VSync signals as inputs. If the S bit is O, the DP operates as a Master with HSync and VSync as outputs.
The 82786 could address 4 Mbytes of memory. In those days, most systems divided memory in at least two segments, in the case of the 82786 graphics memory, which used the DRAM/VRAM controller, and external system memory. Dividing memory can enhance the performance of graphics applications. The DRAM/VRAM controller allowed faster access to graphics memory than external system memory because it did not encounter contention from the CPU. The CPU accessed system memory and executed programs simultaneously, while the 82786 accessed graphics memory and executed its commands.
However, when performance was not critical, the 82786 and CPU could share the same memory with the integral 82786 DRAM/VRAM controller managing memory accesses. With this configuration, target applications had to be able to tolerate the decreased bandwidth of system memory.
Intel sold the chip as a merchant part and independent AIB suppliers built boards with it. in 1987 two companies were offering three AIBs using the 82786, and by 1988 ten companies were offering 15 AIBs using the chip. The chip wasn’t very powerful compared to others that entered the market, most noteworthy being Texas Instruments’ TSM34010, nor as popular as the IBM VGA and its many clones. Intel; withdrew the chip with the introduction of the 86486 microprocessor in 1989.
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.. >> Library: Article Series
.. .. >> Series: The Graphics Chip Chronicles
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