Clock source
Timing diagram
Conventional clock-fail detectors use silicon delay lines and flip-flops to detect stuck-at-high and stuck-at-low fault conditions in a clock source. Because commercial delay-line devices typically only offer taps ranging from 5 to 500 ns, this approach works best for high-frequency clocks. In applications involving lower frequencies, it may require the cascading of several delay-line ICs to span several clock periods.
The circuit in Figure 1 avoids the delay-line IC altogether, using a second clock source instead. CLOCK1 or its inverse holds the flip-flops preset so the output nCLKF remains logic one as long as the clock continues toggling. If the clock fails in stuck-low mode, CLOCK2 shifts a logic zero through flip-flop pair FF3-FF4, driving nCLKF low. Similarly, if CLOCK1 fails in stuck-high mode, a zero shifts through FF1-FF2.
So in both cases after two rising edges of CLOCK2, nCLKF signals the failure by going low. The only constraints are the frequency of CLOCK2, which must be always less than that of CLOCK1, and the fact that CLOCK2 does not depend on CLOCK1.
The timing diagram in Figure 2 shows how the detect signal works with CLOCK1 at100 kHz and CLOCK2 at 10 kHz. The higher the frequency for CLOCK2, the faster the detector will react.