Is PXI Express Overkill For Boundary Scan?

Just as PXI was developed as an extension of PCI to satisfy special requirements in the test and measurement industry, PXI Express is based on PCI Express and provides respective extensions to that standard.1,2 Because of that tight relationship, future improvements in PCI Express also will be available in PXI Express.

PXI Express allows the creation of state-of-the-art test systems with the highest system throughput in application areas such as real-time RF or video processing. However, other test and measurement applications can benefit from this gain in system throughput. Applications that have been available only in the PCI Express realm now can be realized in PXI by means of PXI Express systems.

Boundary Scan and PXI Express

Being well-established as a valuable test and debug access methodology in the electronics industry, boundary scan as defined in IEEE 1149.1 can be implemented in test systems based on various hardware platforms. Some boundary scan applications such as in-system programming of flash devices, memory cluster testing of complex memory devices, and functional test applications using boundary scan cells can require enormous throughput.3 Consequently, the tester hardware platform must provide the appropriate bandwidth, something serial bus systems such as USB at a maximum of 480 Mb/s and parallel platforms such as PCI with 127 MB/s may not be able to satisfy.

PXI Express combines the benefits of a modular platform featuring test-specific capabilities not available in a PC-based environment with the high-performance bandwidth of the PCI Express bus. This enables the creation of powerful but compact, flexible automated test systems that combine the versatility of functional test equipment with the embedded test access and diagnostic capabilities of boundary scan. Integrating functional test and boundary scan access in a PXI Express environment enables new test, debug, and emulation applications.

Boundary scan has been implemented in PXI-based test equipment for many years. The actual speed improvement for boundary scan applications gained from the additional bandwidth provided by PXI Express depends on the boundary scan controller performance, the type of boundary scan application, and the boundary scan resources on the UUT.

PXI Express provides up to 2-GB/s dedicated bandwidth per slot, which a PXI Express-based boundary scan controller could use. Due to the software compatibility between PXI and PXI Express, upgrading a PXI system to a PXI Express-based test system should be effortless.

An Application Example

Let us look at an example UUT: a board design contains six boundary scan devices, two SDRAM devices, four DDR2 SDRAM devices, two flash EEPROMs (16 x 2 Mb), several buffers and simple logic gates, and a variety of passive components (Table 1).For this analysis, we will look at in-system programming of flash devices.

Table 1. Example UUT BSR = Boundary Scan Register

If all boundary scan-compliant devices are connected in one scan chain, the total number of boundary scan cells in the chain is 4,929. The maximum test clock (TCK) frequency is 10 MHz. The slowest device in the chain determines the maximum TCK frequency. In reality, the maximum TCK may be even less if the scan chain is not well designed.

Based on these numbers, it takes about 493 ï¿½s to shift through the boundary scan chain, ignoring any software or hardware overhead. With this long shift time, the maximum sample or update rate on a boundary scan I/O pin would be about 2 kHz. The only way to improve that throughput on the I/O pins would be to shorten the boundary scan chain by putting some devices in bypass mode.

The flash devices on this UUT require six shift cycles on the boundary scan chain to program one word. The 32-Mb flash memory devices on the UUT are programmed in 16-b words, requiring 2,048,000 programming cycles.

Assuming that only the DSP and the CPU need to be in the test mode and the other four devices are in bypass mode in a separate scan chain, the number of bits to transmit per shift cycle is 1,072 b (302 + 769), and the maximum TCK frequency is 20 MHz. The shift time for each vector would be 53.6 ï¿½s, the total shift time 658.64 s:

tshiftT = 53.6 ï¿½s x 6 x 2,048,000 = 658.64 s

The total amount of data to be transmitted would be 13 Gb:

DATAtransmit = 1,072 bit x 6 x 2,048,000 = 13,172,736,000 b

This amount of data will impose a noticeable overhead on the execution time of the flash programming application.

PCI and PXI have a bandwidth of 127 MB/s or approximately 1 Gb/s. In practice, it sometimes takes more than one PCI cycle to transmit 32 b, so the effective throughput would be less that 1 Gb/s. Even so, the overhead for data transmission (overheadPCI) would be only about 2% of the shift time needed: tPCI transmit = 13 Gb/1 Gb/s = 13 s overheadPCI = 13 x 100%/658.64 = 2%

PCI Express and PXI Express have a bandwidth of 2.5 Gb/s in a x1 link. Assume that, in practice, the effective bandwidth for the transmission of the boundary scan vectors would be more like 2 Gb/s. This would still mean an improvement of 100% compared to PCI/PXI, resulting in an overhead of only about 1% of the shift time.

This overhead becomes more noticeable the faster the TCK gets. For ex- ample, for a TCK of 100 MHz, the transmission of data over the host bus would be 10% and 5% for PCI/PXI and PCI Express/PXI Express, respectively.

In practice, 1 byte often transmits only one TCK cycle on the host bus. The actual amount of data required to transmit one TCK cycle from the tester software to the UUT depends on the boundary scan controller implementation. This would mean that a 32-b PCI cycle does not transmit 32 TCKs but only four, effectively reducing the throughput to 130 Mb/s.

This would translate into a data transmission overhead of about 16% for PCI with a TCK on the UUT of 20 MHz. For a x1 PXI Express link, the overhead can be scaled in a similar way to approximately 8%.

On the other hand, considering that PCI requires two to 10 clocks to transmit one write cycle for one read cycle, the data transmission overhead on a PCI-based test system would increase in the neighborhood of 4% to 20% of the shift time on the UUT. This effect only is true for PCI signaling, not for PCI Express.

In effect, the actual overhead for data transmission on PCI compared to shift time on the UUT lies somewhere between 64% and 320% compared to about 8% for a PCI Express x1 link for this example. So, in real-world implementations, the host bus bandwidth can have a big impact on the run time of data-intensive boundary scan applications such as in-system programming of flash devices.

Table 2 compares the data transmission times for PXI and PXI Express platforms. Even though the numbers given are only representative for specific types of applications, it becomes obvious that PXI Express can provide a dramatic improvement in throughput for data-intensive boundary scan applications.

Table 2. Comparison of Data Transmission Times for PXI and PXI Express ï¿½

Summary For many boundary scan applications, the performance of PCI/PXI is sufficient. However, data-intensive applications such as in-system programming of flash devices can benefit from the higher bandwidth provided by PXI Express.

We can expect boundary scan-compliant devices to become faster and offer more advanced test features in the future. This development and the migration of functional test applications into the boundary scan domain will generate demand for ATE featuring the modularity, versatility, and bandwidth of PXI Express.

References 1. PXI Express Specifications, PXI-5 PXI Express Hardware Specification and PXI-6 PXI Express Software Specification, 2005, PXI System Alliance. 2. PCI Express Specification, PCI-SIG. 3. IEEE 1149.1-2001, IEEE Standard Test Access Port and Boundary Scan Architecture, 2001.

About the Author Heiko Ehrenberg is managing director of operations at GOEPEL Electronics LLC. After graduating from the University of Applied Sciences at Mittweida, Germany, in 1996, he was employed by GOEPEL electronic GmbH in Jena, Germany, as an application engineer for JTAG/boundary scan. In 1998, Mr. Ehrenberg transferred to the companyï¿½s U.S. subsidiary and was promoted a year later to his current position. GOEPEL Electronics LLC, 9600 Great Hills Trail, 150W, Austin, TX 78759, 512-502-3010; e-mail: [email protected]