What’s the Difference Between VHDL, Verilog, and SystemVerilog?
Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, Verilog, and SystemVerilog. They differ from software programming languages because they include a means of describing propagation time and signal strengths. These days, it would be impossible to design a complex system on a chip (SoC) for a mobile device or any other consumer electronics product without an HDL.
Each of the three HDLs has its own distinct style. VHDL and Verilog implement register-transfer-level (RTL) abstractions. When they were first introduced in the late 1980s, they were considered breakthrough technologies because they enabled engineers to work at a higher level of abstraction with RTL simulators. Previously, engineers simulated their designs at the schematic or gate level.
SystemVerilog was developed to provide an evolutionary path from VHDL and Verilog to support the complexities of SoC designs. It’s a bit of a hybrid—the language combines HDLs and a hardware verification language using extensions to Verilog, plus it takes an object-oriented programming approach. SystemVerilog includes capabilities for testbench development and assertion-based formal verification.
The U.S. Department of Defense funded VHDL, and Gateway Design Automation developed Verilog to drive the Verilog simulator. Cadence Design Systems, once it acquired Gateway, placed the Verilog HDL into the public domain and it became an industry standard.
In the early 1990s, the electronics industry was forced to contend with the “language wars,” where competing factions in either the VHDL or Verilog camp competed for an engineer’s mindset and desktop. Both languages survived and now coexist, often in the same design flow.
Co-Design designed SystemVerilog, initially known as SUPERLOG. After Synopsys acquired Co-Design, SUPERLOG/SystemVerilog was placed in the public domain as well.
All three are IEEE industry standards –– VHDL is IEEE 1076-2008, Verilog is IEEE 1364-2005 and SystemVerilog is IEEE 1800-2012. The IEEE works cooperatively with the industry standards organization Accellera, which acts as its steward and develops many of IEEE’s technology standards for system-level design, modeling, and verification.
My company, Verific Design Automation, has built parsers and elaborators for VHDL, Verilog, and SystemVerilog since 1999.
This file type includes high resolution graphics and schematics when applicable.
Comparing VHDL, Verilog, SystemVerilog
VHDL and Verilog are considered general-purpose digital design languages, while SystemVerilog represents an enhanced version of Verilog. Each has its own style and characteristics. VHDL has roots in the Ada programming language in both concept and syntax, while Verilog’s roots can be tracked back to an early HDL called Hilo and the C programming language.
With Verilog and VHDL, engineers can represent the desired functionality as a software program. Then the model is simulated to confirm the design will work as intended. Any problems can be corrected in the model, and simulation will verify the correction.
VHDL is a rich and strongly typed language, deterministic and more verbose than Verilog. As a result, designs written in VHDL are considered self-documenting. Its syntax is non-C-like and engineers working in VHDL need to do extra coding to convert from one data type to another. VHDL often catches errors missed by Verilog. VHDL emphasizes unambiguous semantics and allows portability between tools.
Sample VHDL Code
reg1: process (rst, clk) begin if rst = '1' then q_reg <= (others => '0'); q_i <= (others => '0'); elsif rising_edge(clk) then if s_l = '1' then q_i(0) <= q_i(7); loop1: for i in 6 downto 0 loop q_i(i + 1) <= q_i(i); end loop loop1; q_reg <= y; else q_i <= q_reg; q_reg <= y; end if; end if; end process reg1;
Verilog is weakly typed and more concise with efficient notation. It is deterministic. All data types are predefined in Verilog and each has a bit-level representation. Syntax is C-like.
Sample Verilog Code
always @(posedge CLK or posedge RST) begin if (RST) begin q_reg = 0; Q = 0; end else if (S_L) begin Q[7:0] = {Q[6:0],Q[7]}; q_reg = Y; end else begin Q = q_reg; q_reg = Y; end end
SystemVerilog includes a set of extensions to the Verilog HDL to help engineers design and verify larger and more complex designs. In fact, many industry watchers consider it the first Hardware Description and Verification Language (HDVL), because it combines VHDL and Verilog features with those of Hardware Verification Languages (HVLs) Vera and e, as well as C and C++. It’s targeted at RTL coding, using constrained random techniques for assertion-based and coverage-driven verification.
Sample SystemVerilog Code
property p_push_error; @ (posedge clk) not (b_if.push && b_if.full && !b_if.pop); endproperty : p_push_error ap_push_error_1 : assert property (p_push_error); property p_pop_error; @ (posedge clk) not (b_if.pop && b_if.empty); endproperty : p_pop_error ap_pop_error_1 : assert property (p_pop_error); always_ff @ (posedge clk) begin b_if.error <= (b_if.pop && b_if.empty) || (b_if.push && b_if.full && !b_if.pop);
Because of its structure, VDHL catches most errors early in the design process. Verilog, on the other hand, enables engineers to quickly write models. SystemVerilog attempts to capture the best features of both, and includes features of HVLs to support testbench development and formal verification techniques.
Conclusion
The “language war” days are long over, as engineering teams worldwide effectively employ VHDL, Verilog and SystemVerilog for their SoC design needs. This overview provides a glimpse at the differences between the three. In general, SystemVerilog can help with both design and verification. Design tools from electronic-design-automation (EDA) companies can combine VHDL and Verilog to suit all types of engineering requirements.