Domain-Specific Verification Method Plugs And Plays With Testbench Tools

May 27, 2002
Verification engineers need productivity if they're to tackle system-on-a-chip (SoC) functional verification. A new methodology centering on application-domain-specific verification promises a 10× to 25× productivity improvement compared...

Verification engineers need productivity if they're to tackle system-on-a-chip (SoC) functional verification. A new methodology centering on application-domain-specific verification promises a 10× to 25× productivity improvement compared with methods based on hardware description languages (HDLs).

Qualis Design's Domain Verification Component (DVC) technology addresses three critical aspects of functional verification: protocol-specific stimulus generation, automated response checking, and extraction of test-coverage metrics (see the figure).

The DVCs run as an application layer atop Synopsys' VERA and Verisity's Specman Elite testbench auto-mation tools to drastically reduce the time required to create complex verification environments for domain-specific designs. Available now within Qualis' networking family are DVCs for Sonet, ATM, Utopia 1 and 2, SPI 4.2, and Ethernet. Other networking, wireless, and core interconnect DVCs are to come.

The DVC test-stimulus generation blocks conform to industry-standard protocols and interfaces. They allow full random, constrained random, and directed test generation. Similarly, the response-checking blocks support standard protocols and interfaces to automate large regression simulation runs.

Test coverage blocks track coverage metrics by extracting coverage statistics from the environment and simulator, allowing users to accurately assess the level of test case coverage. The Qualis methodology's level-independent architecture supports advanced verification capabilities for block, ASIC/SoC, system, and board-level simulation.

Visit www.qualis.com for details.

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.

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